tag: DFT

Demand for IC Resilience Drives Methodology Changes
By Ann Mutschler - 25 Mar, 2021 - Comments: 0

Applications that demand safety, security, and resilience are driving new ways of thinking about design, verification, and the long-term reliability of chips on a mass scale. The need is growing for chips that can process more data faster, over longer periods of time, and often within a shrinking power budget. That, in turn, is forcing changes at multiple levels, at the architecture, design,... » read more

Hunting For Open Defects In Advanced Packages
By Anne Meixner - 17 Mar, 2021 - Comments: 5

Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Preventing Chips From Burning Up During Test
By Bryon Moyer - 09 Mar, 2021 - Comments: 1

It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

Design Issues For Chips Over Longer Lifetimes
By Ed Sperling - 08 Mar, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Automotive Test Moves In-System
By Bryon Moyer - 09 Feb, 2021 - Comments: 1

With the electrification of automobiles, it’s not enough to test the new electronics thoroughly at the end of the manufacturing process. Safety standards now require that tests be performed live, in the field, with contingency plans should a test fail. “We see clear demand from the automotive semiconductor supply chain for design functionality specifically aimed at in-system monitoring,�... » read more

Have It All With No-Compromise DFT
By Geir Eide - 28 Jan, 2021 - Comments: 0

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs but can become problematic with an increase in the number of cores and the design complexity on today’s SoCs. The next revol... » read more

Streaming Scan Network
By Siemens EDA - 27 Jan, 2021 - Comments: 0

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

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