Resetting Expectations On Multi-Patterning Decomposition And Checking

By David Abercrombie - 22 Oct, 2015 - Comments: 0

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

Double Patterning Custom Design And Debug

By Mentor, a Siemens Business - 22 Oct, 2015 - Comments: 0

Litho-Etch-Litho-Etch (LELE) double pattern (DP) processing affects many aspects of the design flow at/below the 20 nm node level. This can be very disruptive for the custom designer, impacting basic cell design strategy, layout rules and debug as well as parasitic extraction. This paper discusses how to deal with these impacts, avoid common design mistakes, and debug quickly and accurately. ... » read more

EUV: Cost Killer Or Savior?

By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Case Studies in P&R Double-Patterning Debug

By David Abercrombie - 20 Aug, 2015 - Comments: 0

In my last article, we looked at some case studies of the unique types of issues related to double patterning (DP) that place and route (P&R) and chip finishing engineers have to deal with. I’ve got some more interesting case studies to show you this time. In modern P&R designs, the metal routes on a particular layer are unidirectional (or at least primarily unidirectional). Long p... » read more

Rethinking Manufacturing Models

By Ed Sperling - 23 Jul, 2015 - Comments: 0

The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry. Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes m... » read more

Inside Samsung’s Foundry Biz

By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at [getentity id="22865" e_name="Samsung Semiconductor"]; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion. SE: The foundry business has alway... » read more

Tech Talk: 22nm FD-SOI

By Ed Sperling - 13 Jul, 2015 - Comments: 0

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

Litho Challenges Break The Design-Process Wall

By Katherine Derbyshire - 22 Jun, 2015 - Comments: 3

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process. Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancemen... » read more

Case Studies In Double-Patterning Debug

By David Abercrombie - 18 Jun, 2015 - Comments: 0

Double patterning (DP) impacts just about every part of the design and manufacturing flows. However, the kinds of issues you encounter, the way they manifest themselves, and the ideal way to address them may be very different in different parts of these flows. I feel like I have spent a lot of time the last six months or so working with place and route (P&R) and chip finishing engineers on DP i... » read more

The Bumpy Road To 10nm FinFETs

By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

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Knowledge Centers
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