tag: DRAM

Taming Novel NVM Non-Determinism
By Bryon Moyer - 10 Mar, 2020 - Comments: 1

New memory technologies may have non-deterministic characteristics that add calibration to the test burden — and may require recalibration during their lifetime. Many of these memories are in development as a result of the search for a storage-class memory (SCM) technology that can bridge the gap between larger, slower memories like flash and faster DRAM memory. There are several approache... » read more

Enterprise-Class DRAM Reliability
By Ed Sperling - 06 Mar, 2020 - Comments: 0

Brett Murdock, product manager for memory interfaces at Synopsys, examines demand for DDR5 and DDR4 in both on-premise and cloud implementations, what features are available for which versions, how they affect performance and power, how ECC is implemented, and how the data moves throughout these systems. » read more

An Increasingly Complicated Relationship With Memory
By Brian Bailey - 27 Feb, 2020 - Comments: 4

The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

LPDDR4/4X DRAM Variants and Possible System Configurations
By Synopsys - 26 Feb, 2020 - Comments: 0

LPDDR is the de-facto standard for main-memory targeting mobile applications such as smartphones and tablets. Low-Power Double Data Rate Synchronous Dynamic Random Access Memories (LPDDR SDRAMs) or DRAMS offer high-performance while consuming significantly lower power than standard DDR memories, such as DDR5/4/3, which are ideal for systems requiring large memory capacity. For this reason, LPDD... » read more

Chiplet Momentum Rising
By Mark LaPedus - 26 Feb, 2020 - Comments: 0

The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are rallying around the chiplet model, including AMD, Intel and TSMC. In addition, there is a new U.S. Department of Defense (DoD) initiative. The goal is to speed up time to market and reduce the cost... » read more

2020 IC Outlook: Uncertainty
By Mark LaPedus - 24 Feb, 2020 - Comments: 0

After a downturn in 2019, the semiconductor and equipment industries looked promising at the start of 2020. In 2019, the downturn was primarily due to the memory markets, namely DRAM and NAND. Both DRAM and NAND saw lackluster demand and falling prices last year. At the start of 2020, though, the memory markets were beginning to recover. Unlike memory, the logic and foundry markets were s... » read more

Moore And More
By Paul McLellan - 13 Feb, 2020 - Comments: 0

For more than 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law — or so it seemed. In reality, there were three laws rolled up into one: Each process generation would have a higher clock speed at the same power. This was not discovered by Moore, but by Dennard, who also invented the DRAM. Process generations continue to get faster and lower power, but the power... » read more

Software In Inference Accelerators
By Ed Sperling - 10 Feb, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance
By Taeyon (TY) Oh - 03 Feb, 2020 - Comments: 0

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
By Technical Paper Link - 31 Dec, 2019 - Comments: 0

Abstract "It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, the memory access patterns of prevalent and... » read more

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