Predictions: Manufacturing, Devices And Companies

By Brian Bailey - 18 Jan, 2018 - Comments: 0

Some predictions are just wishful thinking, but most of these are a lot more thoughtful. They project what needs to happen for various markets or products to become successful. Those far reaching predictions may not fully happen within 2018, but we give everyone the chance to note the progress made towards their predictions at the end of the year. (See Reflection On 2017: Design And EDA and Man... » read more

Challenges Mount For Photomasks

By Mark LaPedus - 21 Sep, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at [getentity id="22817" e_name="Applied Materials"]; Weston Sousa, general manager of the Reticle Products Division at [getentity id="22876" commen... » read more

Securing Chips During Manufacturing

By Ed Sperling - 07 Jul, 2016 - Comments: 0

David Lam, chairman of Multibeam, sat down with Semiconductor Engineering to talk about how next-gen lithography tools can be used to prevent cyber attacks and counterfeiting of hardware. SE: How did you get into the anti-counterfeiting business? Lam: About three years ago we were working with some customers that were troubled by the counterfeiting problem. We became aware of that sense o... » read more

Behind The Scenes In Nanoimprint Lithography

By Jan Willis - 17 Mar, 2016 - Comments: 0

Doug Resnick, VP of marketing and business development at Canon Nanotechnologies, talks about why Canon bought Molecular Imprints, the surprises behind that acquisition, and the problems faced by the semconductor industry moving forward. [youtube vid=NJTxFu-_6GI] » read more

Complementary E Beam Lithography

By eBeam Initiative - 19 Aug, 2015 - Comments: 0

Multibeam Chairman David Lam looks at complementary E-Beam lithography (CEBL) and the impact of 1D design and pitch division. [youtube vid=nyvplBl4HA4] » read more

Tech Talk: Wafer Plane Analysis

By Ed Sperling - 23 Jul, 2015 - Comments: 0

Leo Pang, executive vice president at D2S, talks about the problems of patterning at 40nm and below and how to deal with them more effectively using existing equipment. [youtube vid=FbRyhw2q3fE] » read more

3D Effects At 20nm And Beyond

By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Tech Talk: Moore’s Law

By Ed Sperling - 16 Mar, 2015 - Comments: 0

Aki Fujimara, CEO of D2S, talks with Semiconductor Engineering about the the technical challenges of scaling device and functionality, and the economics on cost per gate. [youtube vid=hBXtSCRbR64] » read more

Tech Talk: Photomask Challenges

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

GlobalFoundries' Bob Pack talks with Semiconductor Engineering about new problems experienced by photomask shops and how does lithography affects it all. [youtube vid=8hJwVhaZhFc] » read more

We Have Reached The Tipping Point For Simulation-Based Mask Data Preparation

By Aki Fujimura - 13 Nov, 2014 - Comments: 0

Since the beginning of the semiconductor industry, mask-data preparation (MDP) and mask verification (MV) have been shape-based: each shape has been treated as an entity unto itself, and if each isolated shape was correct, the mask was correct. This context independence is a critical assumption for conventional fracturing. However, as line/space measurements (L:S) fall below 50nm, shape-ba... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?