EDA Grabs Bigger Slice Of Chip Market

By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Chip Industry In Rapid Transition

By Ed Sperling - 09 Jan, 2019 - Comments: 0

Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

Is Cloud Computing Suitable for Chip Design?

By Brian Bailey - 27 Sep, 2018 - Comments: 2

Is semiconductor design being left behind in a cloud-dominated world? Finance, CRM, office applications and many other sectors have made the switch to a cloud-based computing environment, but the EDA industry and its users have hardly started the migration. Are EDA needs and concerns that different from everyone else? We are starting to see announcements from EDA companies, but few cheerleaders... » read more

Cracking The Auto IC Market

By Ann Mutschler - 06 Sep, 2018 - Comments: 0

The market for automotive electronics is booming, and it has set off a global scramble among established chipmakers and startups. What's becoming clear, though, is that not everyone understands just how different automotive is from the mobile market. Mobile is still the highest-volume market for semiconductors, but the growth has flattened. In contrast, the value of the automotive electronic... » read more

Do Parallel Tools Make Sense?

By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

By Tom Fitzpatrick - 09 Aug, 2018 - Comments: 0

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

The Future Is Bright: DARPA Is Driving Electronic Resurgence

By Frank Schirrmeister - 26 Jul, 2018 - Comments: 0

This week, DARPA ran the Electronics Resurgence Initiative (ERI) Summit in San Francisco, and while we are certainly staring at some daunting challenges to continue the fast-paced development in electronics, it looks like the future actually looks quite bright. I found myself whistling, “How lucky we are to be alive right now” from Lin-Manuel Miranda’s Hamilton when leaving the stunning P... » read more

Debug Issues Grow At New Nodes

By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

Design Reuse Vs. Abstraction

By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Verification As A Flow (Part 1)

By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: emulation