tag: emulation

Hybrid Emulation Takes Center Stage
By Ann Mutschler - 25 Jul, 2019 - Comments: 0

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

How To Optimize Verification
By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Intelligent System Design—Why The Future Does Need Us!
By Frank Schirrmeister - 27 Jun, 2019 - Comments: 0

The month of June 2019 was very inspiring. At the Design Automation Conference (DAC) in Las Vegas, Cadence launched the next phase of our system-level strategy, dubbed “Intelligent System Design.” Later in the month I got to meet some real-life astronauts at the Paris Air Show in Le Bourget—where we exhibited this year for the first time. All of this made me think about the future. Coinci... » read more

Meanwhile, 35 Years Later…
By Zibi Zalewski - 27 Jun, 2019 - Comments: 0

At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges. We had on display a variety of solutions – both hardware ... » read more

Who’s Responsible For Security Breaches?
By Brian Bailey - 24 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

The Changing Landscape of Hardware-Based Verification And Software Development
By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

Three Tools Help Put Safe Vehicles On The Road
By Richard Pugh - 02 May, 2019 - Comments: 0

By Richard Pugh and Gabriele Pulini As the ultimate systems-of-systems, automated vehicles present an enormous verification task, requiring verification of complex sensing, computing, and actuating functions. This can be accomplished only by virtualizing the entire system: the vehicle and the environment it moves through. It also requires a combination of realistic scenario modeling, hard... » read more

Exascale Emulation Debug Challenges
By Ribhu Mittal - 11 Apr, 2019 - Comments: 0

For years, semiconductor industry surveys have shown that functional verification is the dominant phase in chip development and that debug is the most time-consuming task for verification. The problem is getting worse in today’s era of exascale debug, in which software applications drive tests of more than a billion cycles run in emulation on designs of more than a billion gates. System-on-ch... » read more

The Value Of A Model
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Increased talk about the Digital Twin has brought models to the forefront of the discussion. What are the right models for particular applications? What is the correct level of abstraction? Where do the models come from and how are they maintained? How does one value a model? The semiconductor industry has been reluctant to create any model that is not directly used in the development path. ... » read more

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