Week In Review: Design, Low Power

By Jesse Allen - 20 Jan, 2023 - Comments: 0

Worldwide semiconductor revenue increased 1.1% in 2022 to $601.7 billion, up from $595 billion in 2021, according to preliminary results from Gartner. The combined revenue of the top 25 semiconductor vendors increased 2.8% in 2022 and accounted for 77.5% of the market. The memory segment posted a 10% revenue decrease. Analog showed the strongest growth, up 19% from 2021, followed by discretes, ... » read more

Chip Industry’s Technical Paper Roundup: Jan. 17

By Linda Christensen - 17 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library. [table id=74 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting li... » read more

FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)

By Technical Paper Link - 10 Jan, 2023 - Comments: 0

A technical paper titled "PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM" was published by researchers at ETH Zurich and TOBB University of Economics and Technology. Abstract "Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques in off-the-shelf DRAM dev... » read more

Chip Industry’s Technical Paper Roundup: Jan 3

By Linda Christensen - 03 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=72 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 22 Dec, 2022 - Comments: 0

RISC-V The European Union said it will spend the equivalent of $286.5 million on a high performance computing ecosystem based on RISC-V. According to the call for proposals, the aim of the project is to “establish a partnership between the EuroHPC JU and a consortium of industry, research organizations and institutions in HPC to the development of innovative HPC hardware and software technol... » read more

RISC-V Pushes Into The Mainstream

By Marie C. Baca and Ed Sperling - 21 Dec, 2022 - Comments: 1

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)

By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations" was written by researchers at Computer Security Group (COMSEC), ETH Zurich and Zentel Japan. The paper will be presented at IEEE's Symposium on Security and Privacy in May 2023. "With REGA, we propose the first fully in-DRAM mitigation capable of protecting devices independently from their blas... » read more

Chip Industry’s Technical Paper Roundup: Dec. 20

By Linda Christensen - 20 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=71 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)

By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux

By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

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tag: ETH Zurich

Week In Review: Design, Low Power

Chip Industry’s Technical Paper Roundup: Jan. 17

FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)

Chip Industry’s Technical Paper Roundup: Jan 3

Week In Review: Design, Low Power

RISC-V Pushes Into The Mainstream

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)

Chip Industry’s Technical Paper Roundup: Dec. 20

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux