tag: ETH Zurich

Chip Industry’s Technical Paper Roundup: Oct 25
By Linda Christensen - 25 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=59 /] » read more

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A technical paper titled "RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory" was published by researchers at ETH Zürich, KMUTNB, NTUA, and University of Toronto. Abstract: "Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-graine... » read more

Chip Industry’s Technical Paper Roundup: Oct 18
By Linda Christensen - 18 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=57 /] » read more

Accelerating Off-Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction" was published by researchers at ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS.  The work received a best paper award at MICRO 2022. Abstract "Long-latency load requests continue to limit the performance of high-performance ... » read more

Chip Industry’s Technical Paper Roundup: Oct. 4
By Linda Christensen - 04 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=55 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Adaptive Memristive Hardware
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Technical Paper Roundup: Sept 27
By Linda Christensen - 27 Sep, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=53 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Research Bits: Sept. 20
By Jesse Allen - 20 Sep, 2022 - Comments: 0

Multi-mode memristors Researchers from ETH Zurich, the University of Zurich, and Empa built a new memristor that can operate in multiple modes and could potentially be used to mimic neurons in more applications. “There are different operation modes for memristors, and it is advantageous to be able to use all these modes depending on an artificial neural network’s architecture,” said R... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

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