tag: EUV

Using DSA With EUV
By Ed Sperling - 05 Nov, 2018 - Comments: 1

James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

The Impact of Moore’s Law Ending
By Brian Bailey - 29 Oct, 2018 - Comments: 2

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore's Law is slowing down or ending for many market segments. What isn't clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity. Chip design has faced a number of hurdles just to get ... » read more

Wanted: Mask Equipment for Mature Nodes
By Mark LaPedus - 18 Oct, 2018 - Comments: 0

Rising demand for chips at mature nodes is impacting the photomask supply chain, causing huge demand for trailing-edge masks and a shortfall of older mask equipment. The big issue is the equipment shortfall, which could impact customers on several fronts. Tool shortages could lead to longer mask turnaround times and delivery schedules for chips being developed at 90nm and above, which are bu... » read more

EUV Pellicle, Uptime And Resist Issues Continue
By Mark LaPedus - 26 Sep, 2018 - Comments: 0

Extreme ultraviolet (EUV) lithography is moving closer to realization, but several problems involving scanner uptime, photoresists and pellicles need to be resolved before this long-overdue technology is put into full production. Intel, Samsung and TSMC are hoping to insert EUV into production at 7nm and/or 5nm. While the remaining issues don’t necessarily pre-empt using EUV, they do affec... » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Survey: EUV Optimism Grows
By Mark LaPedus - 17 Sep, 2018 - Comments: 2

The confidence level remains high for extreme ultraviolet (EUV) lithography, although the timing of the insertion remains a moving target, according to a new survey released by the eBeam Initiative. At the same time, the outlook for the overall photomask industry is bullish, according to the survey. On the downside, however, there appears to be no progress in terms of improving mask turnaro... » read more

GF Puts 7nm On Hold
By Mark LaPedus - 27 Aug, 2018 - Comments: 6

GlobalFoundries is putting its 7nm finFET program on hold indefinitely and has dropped plans to pursue technology nodes beyond 7nm. The moves, which mark a major shift in direction for the foundry, involve a headcount reduction of about 5% of its worldwide workforce. At the same time, the company is also moving its ASIC business into a new subsidiary. As a result of GlobalFoundries’ ann... » read more

Blog Review: Aug. 22
By Jesse Allen - 22 Aug, 2018 - Comments: 0

Cadence's Paul McLellan considers how much further we need to go to make EUV work for 5nm, the problem of cost, and ASML's EUV roadmap. In a video, Mentor's Colin Walls explains optimizing data in embedded software with a simple example of two ways to put data in memory and how to decide which is best. Synopsys' Fred Bals provides a rundown of the different types of application security t... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Defect Reduction At 7/5nm
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

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