tag: EUV

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Survey: EUV Optimism Grows
By Mark LaPedus - 17 Sep, 2018 - Comments: 2

The confidence level remains high for extreme ultraviolet (EUV) lithography, although the timing of the insertion remains a moving target, according to a new survey released by the eBeam Initiative. At the same time, the outlook for the overall photomask industry is bullish, according to the survey. On the downside, however, there appears to be no progress in terms of improving mask turnaro... » read more

GF Puts 7nm On Hold
By Mark LaPedus - 27 Aug, 2018 - Comments: 6

GlobalFoundries is putting its 7nm finFET program on hold indefinitely and has dropped plans to pursue technology nodes beyond 7nm. The moves, which mark a major shift in direction for the foundry, involve a headcount reduction of about 5% of its worldwide workforce. At the same time, the company is also moving its ASIC business into a new subsidiary. As a result of GlobalFoundries’ ann... » read more

Blog Review: Aug. 22
By Jesse Allen - 22 Aug, 2018 - Comments: 0

Cadence's Paul McLellan considers how much further we need to go to make EUV work for 5nm, the problem of cost, and ASML's EUV roadmap. In a video, Mentor's Colin Walls explains optimizing data in embedded software with a simple example of two ways to put data in memory and how to decide which is best. Synopsys' Fred Bals provides a rundown of the different types of application security t... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Defect Reduction At 7/5nm
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

7nm Design Challenges
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

What’s Next In R&D?
By Mark LaPedus - 21 Jun, 2018 - Comments: 1

Luc Van den hove, president and chief executive of Imec, sat down with Semiconductor Engineering to discuss R&D challenges and what’s next in the arena. The Belgium R&D organization is working on AI, DNA storage, EUV, semiconductors and other technologies. What follows are excerpts of that conversation. SE: Moore’s Law is slowing down. And it is becoming more expensive to move fr... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

What’s In A Node?
By Sundeep Bajikar - 30 May, 2018 - Comments: 0

In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

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