tag: fan-out wafer-level packaging

Advanced Packaging Moves To Cars
By Ann Mutschler - 07 Aug, 2017 - Comments: 0

By Ann Steffora Mutschler and Ed Sperling As automotive OEMs come up to speed on electrification of vehicles, each at their own pace, they are starting to embrace novel packaging approaches as a way to differentiate themselves in an increasingly competitive market. Wirebond used to dominate this market, where most of the chips were relatively unsophisticated and product cycles were slow�... » read more

Solving The Design And Verification Challenges Of High Density Advanced Packaging
By Mentor, a Siemens Business - 07 Aug, 2017 - Comments: 0

This paper discusses ways in which design teams can apply silicon (IC) type processes to the design and verification of the emerging HDAP packages. High Density Advanced Packaging, or HDAP, is the next-generation architecture for increased functional density, higher performance, lower power, smaller PCB footprints, and thinner profiles. This new “breed” of disruptive packaging technology... » read more

What Does An IoT Chip Look Like?
By Ed Sperling - 19 Jul, 2017 - Comments: 4

By Ed Sperling and Jeff Dorsch Internet of Things chip design sounds like a simple topic on the face of it. Look deeper, though, and it becomes clear there is no single IoT, and certainly no type of chip that will work across the ever-expanding number of applications and markets that collectively make up the IoT. Included under this umbrella term are sensors, various types of processors, ... » read more

28nm Chip-Package Interactions In Large eWLB FO-WLP
By STATS ChipPAC - 10 Jul, 2017 - Comments: 0

To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabl... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

What’s Next In Scaling, Stacking
By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Board Level Reliability Improvement In eWLB
By STATS ChipPAC - 05 Jun, 2017 - Comments: 0

When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibilit... » read more

Tech Talk: System In Package
By Ed Sperling - 05 Jun, 2017 - Comments: 0

ASE fellow and senior technical advisor William Chen talks about advanced packaging options and why they are now so important. » read more

High-Stakes Litho Game
By Ed Sperling - 18 May, 2017 - Comments: 0

The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success. In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems ou... » read more

2.5D, Fan-Out Inspection Issues Grow
By Ed Sperling - 12 May, 2017 - Comments: 0

As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

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