The Increasingly Uneven Race To 3nm/2nm

By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

From FinFETs To Gate-All-Around

By Nerissa Draeger - 19 Nov, 2020 - Comments: 0

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond

By Taigon Song - 27 Sep, 2018 - Comments: 1

When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

What’s After FinFETs?

By Mark LaPedus - 24 Jul, 2017 - Comments: 3

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Samsung Unveils Scaling, Packaging Roadmaps

By Ed Sperling - 24 May, 2017 - Comments: 5

Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

Inside Advanced Patterning

By Mark LaPedus - 15 Dec, 2016 - Comments: 0

Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at [getentity id="22817" e_name="Applied Materials"], sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion. SE: From your standpoint, what are the big... » read more

Deeper Inside Intel

By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

What Transistors Will Look Like At 5nm

By Mark LaPedus - 18 Aug, 2016 - Comments: 3

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Atomic Layer Etch Heats Up

By Mark LaPedus - 29 Jun, 2016 - Comments: 0

The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targete... » read more

5nm Fab Challenges

By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: gate-all-around FET

The Increasingly Uneven Race To 3nm/2nm

From FinFETs To Gate-All-Around

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond

What’s After FinFETs?

Samsung Unveils Scaling, Packaging Roadmaps

Inside Advanced Patterning

Deeper Inside Intel

What Transistors Will Look Like At 5nm

Atomic Layer Etch Heats Up

5nm Fab Challenges

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Baby Steps Toward 3D DRAM

Knowledge Centers
Entities, people and technologies explored