32nm SOI is GloFo Fab 8′s 1st Silicon


Excellent news for the fast-growing SOI community:  the first chips produced at GlobalFoundries’ “Fab 8″ in upstate New York are based on IBM’s latest, 32nm SOI chip technology. In a joint press release, the two companies announced that the chips will be used by customers in networking, gaming and graphics. While the new chips began initial production at IBM’s 300mm fab in East... » read more

How Long Will 28nm Last?


By Ann Steffora Mutschler As soon as a next generation semiconductor manufacturing process node is out, bets are taken on just how long the current advanced process node will last. The 28/20nm transition is no exception. There is certainly a benefit to moving from 40nm to 28nm. The  availability of high-k/metal gate technology offers quite a few advantages in terms of power reduction... » read more

After The Ball Drops


Growing up in New York City leaves lasting memories. The coming holiday season evokes some strong ones. The Christmas tree in Rockefeller Center is an example. Christmas always seemed to radiate in all directions from that huge tree perched above the ice skating rink behind Radio City Music Hall. And then there was the ball dropping on New Year’s Eve in Times Square. For the most part, New Yo... » read more

Experts At The Table: Improving Yield


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instr... » read more

Experts At The Table: Improving Yield


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instr... » read more

Experts At The Table: Improving Yield


y Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instrum... » read more

Limits For TSVs In 3D Stacks?


By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

20nm IP Portability Appears Virtually Impossible


By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

Experts At The Table: Retrofitting Older Process Nodes


By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

Heat Wreaks Havoc


By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

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