Experts At The Table: Multipatterning


By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

CNSE Readying NFX Fab for G450C, EUV Efforts


By David Lammers Two key areas of the semiconductor industry’s future—the 450mm wafer transition and EUV lithography—are the focus of the new NFX (NanoFab Xtension) building now under construction at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. [caption id="attachment_6322" align="alignright" width="120" caption="Alain Kaloyeros"][/caption] T... » read more

Foundries Going Greener


The ongoing push towards green and energy-efficient systems is prompting the silicon foundries to jump on the bandwagon and devise their next-generation processes based on ultra-high voltage technology. For some time, several foundries have offered 1- and 0.5-micron, ultra-high voltage processes with ratings up to 800 volts. But seeking to get a jump for the next wave of designs, the special... » read more

Fabless-Foundry Model Under Stress


By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

The Challenges Of 28nm HKMG


28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt's (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performanc... » read more

GloFo to Fab 28/20nm FD-SOI for ST; ST Tech Open to GF Customers


Two big pieces of news have recently been announced by STMicroelectronics: to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices; ST will open access to its FD-SOI technology to GlobalFoundries’ other customers. The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 2... » read more

Roundtable: DAC Retrospective


Is DAC really a design automation conference, or has it shifted to a design enablement conference due to rising complexity breaking down traditional barriers and silos? Low Power High Performance Engineering talks with Atrenta CTO Bernard Murphy about the changes. [youtube vid=Z_xBaRsC_Hs] » read more

Experts At The Table: IP Subsystems


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that co... » read more

Getting Ready For 20nm


By Ed Sperling and Mark Lapedus Despite hurdles in getting 28nm rolling and predictions that process technology will stick around for years to come, there appears to be rapidly growing interest in 20nm—at least from the design side. This is significant for a couple reasons. First, for most companies 20nm will be the first encounter with double patterning because EUV still is not viable—... » read more

Options And Hurdles Come Into Focus For 3D Stacking


By Mark LaPedus The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market. There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs. The enormous risk to bring ... » read more

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