Aeroacoustics Large-Eddy Simulation of VTOL Aircraft Design

By Cadence - 31 Jul, 2024 - Comments: 0

This conference paper, co-authored by Honda Motor Co. and Cadence, reveals findings on the aeroacoustics predictions of multibladed vertical take-off and landing (VTOL) rotors using large-eddy simulations (LES). Why should you read this white paper? Advanced Simulations: We conducted simulations on VTOL rotors with two to five blades, assessing high-frequency noise predictions. Exp... » read more

GPU Acceleration for Pixel-based Computing in Various Mask Processing and Verification Steps

By D2S - 20 Jun, 2024 - Comments: 0

A technical paper titled "Leaping into the curvy world with GPU accelerated O(p) computing" was published by researchers at D2S, Inc. The papers discusses the advantages of using GPU acceleration for pixel-based computing during various mask processing and verification steps. It found that the O(p) approach for GPU acceleration is effective in handling data processing for curvy masks. F... » read more

Opportunities Grow For GPU Acceleration

By Gregory Haley - 05 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of GPU acceleration on mask design and production and other process technologies, with Aki Fujimura, CEO of D2S; Youping Zhang, head of ASML Brion; Yalin Xiong, senior vice president and general manager of the BBP and reticle products division at KLA; and Kostas Adam, vice president of engineering at Synopsys. W... » read more

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V

By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips

By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

Getting Ready For EUV

By Jan Willis - 06 Sep, 2017 - Comments: 0

The highly anticipated introduction of extreme ultra-violet (EUV) lithography is reflected in recent surveys conducted by the eBeam Initiative, which will be presented on Sept. 11 at the annual Photomask Technology Symposium in Monterey, Calif. There are many changes are coming to the mask industry, in addition to EUV. Those include greater use of inverse-lithography technologies (ILT) and... » read more

The Secret Life Of Accelerators

By Ed Sperling - 27 Jul, 2017 - Comments: 0

Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

Inside Lithography And Masks

By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Big Changes In Patterning

By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Will GPU-Acceleration Mean The End Of Empirical Mask Models?

By Ryan Pearman - 20 Oct, 2016 - Comments: 0

Shrinking mask feature sizes and increasing proximity effects are driving the adoption of simulation-based mask processing. Empirical models have been most widely used to date, because they are faster to simulate. Today, GPU-acceleration is enabling fast simulation using physical models. Does the ability of GPU-acceleration to make physical models a practical solution mean the end of empirical ... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?