5nm Vs. 3nm

By Mark LaPedus - 24 Jun, 2019 - Comments: 16

Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 24 May, 2019 - Comments: 0

Packaging and test In the rankings, ASE was the top OSAT in terms of sales in the first quarter of 2019, according to TrendForce. Amkor and JCET were next in the rankings. “Judging from the falling phone sales 1Q19 impacted by the U.S.-China trade dispute and the oversupply situation in memory markets, the total revenue of the top ten businesses in packaging and testing are predicted to st... » read more

The Arm-Huawei Disconnect

By Ed Sperling - 23 May, 2019 - Comments: 0

Arm's move to stop licensing its processor IP to HiSilicon, the captive chipmaker for Huawei, has set off a panic across the semiconductor industry. While the underlying threat to the entire chip industry is very real, many of the conclusions being drawn about this move are misleading or just plain wrong. When the U.S. government blacklisted Huawei, it imposed export restrictions on shipping... » read more

Aging In Advanced Nodes

By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Using More Verification Cores

By Brian Bailey - 30 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Verification Trends Enabling A 5G Future

By Frank Schirrmeister - 23 Aug, 2018 - Comments: 0

Applications have driven requirements for verification for quite some time now, as I have written previously regarding Aero & Defense, AI and Machine Learning and the Internet of Things. In wireless communication, we are just at the brink of the transition to Fifth Generation Networks, or 5G. This transition will not only lead to new applications and use models that will impact our day-to-d... » read more

Week In Review: Design, Low Power

By Jesse Allen - 10 Aug, 2018 - Comments: 0

Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Toward A 5G, AI-Centric World

By Sundeep Bajikar - 19 Apr, 2018 - Comments: 0

The market environment over the coming years will continue to experience an explosion of data generation from a variety of new sources such as smart cars, smart factories, smart hospitals and smart network infrastructure. Data explosion combined with artificial intelligence (AI) will create a renaissance of computing and storage hardware. Mobile World Congress 2018 (MWC) reinforced this market ... » read more

Cheaper Packaging Options Ahead

By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 05 Jan, 2018 - Comments: 0

Chipmakers Semiconductor IP startup eVaderis has demonstrated a design platform through an ultra-low-power microcontroller (MCU) in Beyond Semiconductor’s BA2X product line. The software, system and memory IP developed by eVaderis make Beyond Semiconductor’s new MCU ideally suited for battery-powered applications in IoT and wearable electronics. By incorporating the latest STT-MRAM tec... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.