One-On-One: Thomas Caulfield


Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Brain-Inspired Computing


Approaching power/performance tradeoffs from an architectural perspective is essential given the complexities of today’s SoCs. And beyond some traditional techniques that I discussed in a recent article, Bernard Murphy, CTO at Atrenta mentioned that there is currently a lot of buzz about using non-Von Neumann architectures — especially for recognition functions (voice, image and text). ... » read more

Week 49: Are We There Yet?


When I was a little kid my parents would pack me and my sister into the car and drive to the Mediterranean for our summer camping vacation. It was quite a haul from our home on the west side of Germany near the border with Belgium to the south of France, and as is true of any long car trip, the last stretch was the hardest. After hours in the backseat, my sister and I would be craning our necks... » read more

Security Progress In Some Places, Not Others


Security is big business, and it's increasingly part of business done between big businesses in the semiconductor market. The deal that was announced this week between NXP and Qualcomm, adding a secure NFC module to the Snapdragon chip, is certainly good business. But what's really interesting about this arrangement is that it was done between two very prominent companies, which saw a potent... » read more

New Robots For The IoT


Until recently, remote telepresence has largely been a fixed screen with a video link between participants, and mostly in business setting. But all of that is about to change once the [getkc id="76" comment="Internet of Things"]/Internet of Everything begins to take root. There is a plethora of development going on in mobile robotic telepresence (MRT). Companies such as iRobot, Cisco, Suitab... » read more

The End Of Silicon?


As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem. In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reduci... » read more

5 Issues Under The Foundry Radar


In the foundry business, the leading-edge segment grabs most, if not all, of the headlines. Foundry vendors, of course, are ramping up 16nm/14nm finFET processes, with 10nm and 7nm in R&D. The leading-edge foundry business is sizable, but it’s not the only thing going on in the competitive arena. In fact, there are battles taking place in many other foundry segments, such as 2.5D/3D packag... » read more

Stacked Die, Phase Two


The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

The Week In Review: Manufacturing


Intel is in talks to buy Altera, according to The Wall Street Journal. If a deal is reached, Intel would enter the FPGA market amid a slowdown in its core processors business. Intel would also secure its largest foundry customer in Altera. For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above wor... » read more

The Week In Review: Design/IoT


Tools Mentor Graphics uncorked its new IC, package, and PCB co-design and optimization product. It includes a formal flow for ball grid array ball-map planning and optimization based on an "intelligent pin" concept and a multi-mode connectivity management system for cross-domain pin-mapping and system level cross-domain logical verification. Synopsys released a new tool for designing ASIP... » read more

← Older posts Newer posts →