tag: IBM

Internet of FD-SOI Things?
By Katherine Derbyshire - 18 Feb, 2016 - Comments: 0

Are fully-depleted silicon-on-insulator (FD-SOI) wafers having a moment? Certainly SOI wafers are not new. Soitec’s SmartCut layer transfer technology was patented in 1994, and wafers with implanted oxide layers were available before that. Still, adoption of SOI wafers has been limited. Though they offer improved device isolation and reduced parasitics, the increased wafer cost has been an ob... » read more

Why Power Modeling Is So Difficult
By Ed Sperling - 15 Feb, 2016 - Comments: 2

Power modeling has been talked about for years and promoted by EDA vendors and chipmakers as an increasingly important tool for advanced designs. But unlike hardware and software modeling, which have been proven to speed time to market for multiple generations of silicon, power modeling has some unique problems that are more difficult to solve. Despite continued development in this field, po... » read more

Will 3D-IC Work?
By Ed Sperling - 11 Feb, 2016 - Comments: 3

Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

Enablement For A Decade Of Innovation
By Frank Schirrmeister - 28 Jan, 2016 - Comments: 0

As I do every January, I am looking back 5, 10, and 15 years to see what predictions did and did not turn out to be right, and how that relates to design technologies enabling those developments. Looking back five years reveals just how key system-development technologies were for what IEEE dubbed the “Top 11 Technologies of the Decade”. Looking back 10 years shows how they enabled communic... » read more

Inside Neuromorphic Computing
By Mark LaPedus - 25 Jan, 2016 - Comments: 2

Semiconductor Engineering sat down to talk about neuromorphic technology with Guy Paillet, chief executive of General Vision. The fabless IC design house is a pioneer and supplier of neuromorphic chips. What follows are excerpts of that conversation. SE: In 1993, you invented and co-patented a neural networking chip with IBM. Then, you joined General Vision in 1999. Briefly tell us about Gen... » read more

Industry Road Map Under Construction
By Ed Sperling - 21 Jan, 2016 - Comments: 0

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

Why Use A Package?
By Ed Sperling - 21 Jan, 2016 - Comments: 0

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department—and a former fellow and director of the systems scaling technology department at IBM—sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the fut... » read more

Inside AI And Deep Learning
By Mark LaPedus - 21 Jan, 2016 - Comments: 0

Semiconductor Engineering sat down to talk with Dave Schubmehl, research director for content analytics, discovery and cognitive systems at International Data Corp. (IDC), a market research firm. Schubmehl’s research covers information access, artificial intelligence, cognitive computing, deep learning, machine learning and other topics. He also addressed neuromorphic technology. What follows... » read more

Will 5nm Happen?
By Mark LaPedus - 20 Jan, 2016 - Comments: 7

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Advanced Packaging Is Real. Now What?
By Ed Sperling - 14 Jan, 2016 - Comments: 0

For the past five years, it's been clear that 2.5D, fan-outs and other forms of system-in-package were on the horizon. Exactly when they would arrive no one knew. The most common prediction was that the timing would depend on when one of the big chipmakers decided to go down that route. The theory was that the remainder of the industry would follow, ecosystem issues would be sorted out—partic... » read more

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