China Speeds Up Advanced Chip Development

By Mark LaPedus - 22 Jun, 2020 - Comments: 18

China is accelerating its efforts to advance its domestic semiconductor industry, amid ongoing trade tensions with the West, in hopes of becoming more self-sufficient. The country is still behind in IC technology and is nowhere close to being self-reliant, but it is making noticeable progress. Until recently, China’s domestic chipmakers were stuck with mature foundry processes with no pres... » read more

The Next Advanced Packages

By Mark LaPedus - 18 Jun, 2020 - Comments: 4

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

ESD Requirements Are Changing

By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)

By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

Manufacturing Bits: May 26

By Mark LaPedus - 26 May, 2020 - Comments: 0

7-level nanosheets The 2020 Symposia on VLSI Technology & Circuits for the first time will be held as a virtual conference. The event, to be held from June 15-18, is organized around the theme “The Next 40 Years of VLSI for Ubiquitous Intelligence.” Among the papers at the event include advanced nanosheet transistors, 3D stacked memory devices and even an artificial iris. At the ... » read more

EUV’s Uncertain Future At 3nm And Below

By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

Compute-In Memory Accelerators Up-End Network Design Tradeoffs

By Katherine Derbyshire - 21 May, 2020 - Comments: 0

An explosion in the amount of data, coupled with the negative impact on performance and power for moving that data, is rekindling interest around in-memory processing as an alternative to moving data back and forth between the memory and the processor. Compute-in-memory (CIM) arrays based on either conventional memory elements like DRAM and NAND flash, as well as emerging non-volatile memori... » read more

Manufacturing Bits: May 19

By Mark LaPedus - 19 May, 2020 - Comments: 0

Virus simulations Using an advanced building simulator and testbed, Lawrence Berkeley National Laboratory (Berkeley Lab) is launching a study of the risk of airborne transmission of viruses in buildings. Researchers will also explore the ways to mitigate those risks. The experiments will take place in Berkeley Lab’s FLEXLAB, which is an advanced building simulator. Used by builders, archi... » read more

Making Sense Of PUFs

By Bryon Moyer - 07 May, 2020 - Comments: 3

As security becomes a principal design consideration, physically unclonable functions (PUFs) are seeing renewed interest as new players emerge onto the market. PUFs can play a central role in hardware roots of trust (HRoTs), but the messaging in the market can make it confusing to understand the different types of PUF as well as their pros and cons. PUFs leverage some uncertain aspect of som... » read more

Manufacturing Bits: May 5

By Mark LaPedus - 05 May, 2020 - Comments: 0

Spiking neural network radar chip Imec has developed what the R&D organization says is the world’s first chip that processes radar signals using a spiking recurrent neural network. Initially, the chip from Imec is designed for low-power, anti-collision radar systems in drones. Neural networks are used in the field of machine learning. A subset of AI, machine learning utilizes a neu... » read more

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tag: imec

China Speeds Up Advanced Chip Development

The Next Advanced Packages

ESD Requirements Are Changing

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)

Manufacturing Bits: May 26

EUV’s Uncertain Future At 3nm And Below

Compute-In Memory Accelerators Up-End Network Design Tradeoffs

Manufacturing Bits: May 19

Making Sense Of PUFs

Manufacturing Bits: May 5

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