tag: imec

Finding, Predicting EUV Stochastic Defects
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Manufacturing Bits: May 25
By Mark LaPedus - 25 May, 2021 - Comments: 0

Higher voltage GaN Imec and Aixtron have demonstrated the ability to extend gallium-nitride (GaN) to new voltage levels in the power semiconductor market, enabling the technology to compete in much broader segments. Imec and Aixtron have demonstrated epitaxial growth of GaN buffer layers qualified for 1,200-volt applications on specialized 200mm substrates with a hard breakdown exceeding 1,... » read more

Manufacturing Bits: April 27
By Mark LaPedus - 27 Apr, 2021 - Comments: 0

Next-gen neuromorphic computing The European Union (EU) has launched a new project to develop next-generation devices for neuromorphic computing systems. The project, called MeM-Scales, plans to develop a novel class of algorithms, devices, and circuits that reproduce multi-timescale processing of biological neural systems. The results will be used to build neuromorphic computing systems th... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 23 Apr, 2021 - Comments: 0

Chipmakers and OEMs Several foundry vendors are building new fabs. The memory vendors, such as Samsung and SK Hynix, are also building new capacity. In another example, Taiwan DRAM supplier Nanya Technology plans to construct a new 300mm fab in the Taishan Nanlin Technology Park in New Taipei City. The plant will produce DRAMs with Nanya’s in-house developed 10nm-class process technologies a... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

EUV Pellicles Finally Ready
By Mark LaPedus - 22 Mar, 2021 - Comments: 0

After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips. At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-gen... » read more

Chasing After Carbon Nanotube FETs
By Mark LaPedus - 18 Mar, 2021 - Comments: 6

Carbon nanotube transistors are finally making progress for potential use in advanced logic chips after nearly a quarter century in R&D. The question now is whether they will move out of the lab and into the fab. Several government agencies, companies, foundries, and universities over the years have been developing, and are now making advancements with carbon nanotube field-effect transi... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing
By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

The Future Of FinFETs At 5nm And Beyond
By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more

Making Sense Of New Edge-Inference Architectures
By Bryon Moyer - 04 Mar, 2021 - Comments: 0

New edge-inference machine-learning architectures have been arriving at an astounding rate over the last year. Making sense of them all is a challenge. To begin with, not all ML architectures are alike. One of the complicating factors in understanding the different machine-learning architectures is the nomenclature used to describe them. You’ll see terms like “sea-of-MACs,” “systolic... » read more

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