tag: IP

Unlocking Efficiency: The Power Of IP Blocks In Silicon Chip Design
By Amit Varde - 14 Sep, 2023 - Comments: 0

The fastest, most efficient and cost-effective way to design silicon is by leveraging intellectual property (IP) blocks. This methodology reduces risk, allows a design team to focus on its own differentiation, and allows scalability. Re-using existing IP offers even more value for design teams. But not every company has embraced the approach. Here’s why you should consider it. To optimize ... » read more

Design Complexity In The Golden Age Of Semiconductors
By Frank Schirrmeister - 24 Aug, 2023 - Comments: 0

While writing last month's blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020 or earlier, but I was too close to the deadline to sit down and make orderly updates to some of the charts. Working day-to-day in the area of SoC integration and networks-on-chips (NoCs), the classic chart based on Karl Rupp's now 50 years of processor data that overlay... » read more

Stop-For-Top IP Model To Replace One-Stop-Shop By 2025… And Support The Creation Of Successful Chiplet Business
By Alphawave Semi - 23 Aug, 2023 - Comments: 0

The One-Stop-Shop model has allowed IP vendors of the 2000’s to create a successful IP business, mostly driven by consumer application, smartphone or Set-Top-Box. The industry has dramatically changed, and in 2020 is now driven by data-centric application (datacenter, AI, networking, HPC…), requiring best-in-class, high-performance IP developed on bleeding edge technology nodes. That’s wh... » read more

Analog IP Reuse
By Benjamin Prautsch - 20 Jul, 2023 - Comments: 0

Analog integrated circuit IP is essential to how microelectronic circuits and systems interact with the environment. It enables things like signal conversion, stable power supply, and communication in state-of-the-art devices. However, designing these critical components – even though they are often a small part of complex chips – is very costly and risk-prone. And in today’s analog field... » read more

EDA, IP Fundamentals Shift As Market Soars
By Ed Sperling - 10 Jul, 2023 - Comments: 0

EDA tools and IP continued their double-digit growth trajectory this year, despite a downturn in consumer electronics and a continued shortage of key components that took a large bite out of the semiconductor market as a whole. A just-released report from the ESD Alliance showed a 12% increase in revenue for Q1, increasing to $3.95 billion compared with $3.53 billion in the same period in 20... » read more

The Design Automation Conference Turns 60! What’s Hot? What’s Next?
By Frank Schirrmeister - 06 Jul, 2023 - Comments: 0

This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call "Electronic Design Automation" (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. Industry luminary Alberto Sangiovanni Vincentelli will give o... » read more

IP Becoming More Complex, More Costly
By Brian Bailey - 25 May, 2023 - Comments: 0

Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the number of companies competing in this market. What constitutes an IP block has changed significantly since the concept was first introduced in the 1990s. What was initially just a piece of RTL (reg... » read more

Can AI Write RTL?
By Brian Bailey - 01 May, 2023 - Comments: 1

Just a few months ago, generative AI was just a promise about what would be possible in the future. Today, nearly everyone with an ounce of curiosity has tried ChatGPT. Most people appear to be somewhat impressed with what it can do, but at the same time see the limitations that it has. As Dean Drako, founder of several companies, told me: "Recently, I needed to write a patent. I described t... » read more

Pre-Layout, Post-Layout Circuit Reliability
By Siemens EDA - 26 Apr, 2023 - Comments: 0

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

The Importance Of Metal Stack Compatibility For Semi IP
By Geoff Tate - 02 Mar, 2023 - Comments: 0

Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks. Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more. The most complex, high performance chips, including performance FPGAs, typically use AL... » read more

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