tag: Lam Research

Blog Review: June 6
By Jesse Allen - 06 Jun, 2018 - Comments: 0

In a video, Cadence's Marc Greenberg discusses the advantages and trade-offs of HBM2 and GDDR6, two advanced memory interfaces targeted to the high-performance computing market. Synopsys' Ravindra Aneja takes a look at what's needed for AI-focused hardware designs and how formal can help with the necessary data path verification. In a video, Mentor's Colin Walls explains the challenges of... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 25 May, 2018 - Comments: 0

Chipmakers GlobalFoundries has announced that its 22nm FD-SOI technology platform has been certified to AEC-Q100 Grade 2 for production. As a part of the AEC-Q100 certification, devices must withstand reliability stress tests for an extended period of time and over a wide temperature range in order to achieve Grade 2 certification. Presto Engineering has joined GlobalFoundries’ ecosystem ... » read more

Quantum Effects At 7/5nm And Beyond
By Ed Sperling - 23 May, 2018 - Comments: 5

Quantum effects are becoming more pronounced at the most advanced nodes, causing unusual and sometimes unexpected changes in how electronic devices and signals behave. Quantum effects typically occur well behind the curtain for most of the chip industry, baked into a set of design rules developed from foundry data that most companies never see. This explains why foundries and manufacturing e... » read more

200mm Fab Crunch
By Mark LaPedus - 21 May, 2018 - Comments: 2

Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment, and it shows no sign of letting up. Today, 200mm fab capacity is tight with a similar situation projected for the second half of 2018 and perhaps well into 2019. In fact, 2018 will likely represent the third consecutive year that 200mm fab capacity will be tight. The sam... » read more

FinFET Metrology Challenges Grow
By Mark LaPedus - 17 May, 2018 - Comments: 1

Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

Blog Review: May 2
By Jesse Allen - 02 May, 2018 - Comments: 0

Arm's Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance. Mentor's Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA des... » read more

Advanced 3D Design Technology Co-Optimization For Manufacturability
By Yu De Chen - 30 Apr, 2018 - Comments: 0

By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performanc... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

New Patterning Options Emerging
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Searching For EUV Defects
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

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