tag: lithography

Finding Defects In EUV Masks
By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Multi-Patterning EUV Vs. High-NA EUV
By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Making And Protecting Advanced Masks
By Mark LaPedus - 27 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Using Digital Twins And DL In Lithography
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, looks at the results of inverse lithography technology at advanced nodes using curvilinear patterns, and how that can be combined with a digital twin and deep learning speed up time to market and reduce cost. » read more

Inspecting, Patterning EUV Masks
By Mark LaPedus - 06 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Manufacturing Bits: Sept. 17
By Mark LaPedus - 17 Sep, 2019 - Comments: 0

Full-chip inverse lithography D2S has developed new hardware and software that enables a long-awaited technology--full-chip masks using inverse lithography technology (ILT). For years, ILT has been a promising technology. ILT is a next-generation reticle enhancement technique (RET) that enables an optimal photomask pattern for both optical and extreme ultraviolet (EUV) lithography reticles.... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 30 Aug, 2019 - Comments: 0

Chipmakers GlobalFoundries has filed suits in the U.S. and Germany, alleging that semiconductor manufacturing technologies used by TSMC infringe upon 16 of GF's patents. The suits were filed in the U.S. International Trade Commission (ITC), the U.S. Federal District Courts in the Districts of Delaware and the Western District of Texas, and the Regional Courts of Dusseldorf and Mannheim in Germ... » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster
By Wael elManhawy - 22 Aug, 2019 - Comments: 0

By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more

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