tag: MCM

Die-to-Die Connectivity With High-Speed SerDes PHY IP
By Manuel Mota - 12 Mar, 2020 - Comments: 0

Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

Designing In 4D
By Ed Sperling - 26 Nov, 2019 - Comments: 0

The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

Manufacturing Bits: April 23
By Mark LaPedus - 23 Apr, 2019 - Comments: 0

Sorting nuclei CERN and GSI Darmstadt have begun testing the first of two giant magnets that will serve as part of one of the largest and most complex accelerator facilities in the world. CERN, the European Organization for Nuclear Research, recently obtained two magnets from GSI. The two magnets weigh a total of 27 tons. About 60 more magnets will follow over the next five years. These ... » read more

Cloud Drives Changes In Network Chip Architectures
By Ann Mutschler - 03 Oct, 2018 - Comments: 0

Cloud data centers have changed the networking topology and how data moves throughout a large data center, prompting significant changes in the architecture of the chips used to route that data and raising a whole new set of design challenges. Cloud computing has emerged as the fast growing segment of the data center market. In fact, it is expected to grow three-fold in the next few years, a... » read more

What’s In The Package?
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Advanced Packaging Goes Mainstream
By Ed Sperling - 08 May, 2017 - Comments: 0

The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century. This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and ... » read more

2.5D Creeps Into SoC Designs
By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

EDA Sales Strong Again
By Ed Sperling - 07 Jul, 2015 - Comments: 0

EDA and IP sales were robust again in Q1, up 7.5% to $1.877 billion compared with $1.746 billion in the same period in 2014, according to the EDA Consortium. On the upside, IP revenue rose 19.3% to $618.1 million; services revenue increased 6.8% to $104.4 million; and PCB and multi-chip module revenue increased 1.1% to $161.5 million. On the downside, CAE—the largest single category—... » read more

Pushing The Limits
By Ed Sperling - 13 Jun, 2013 - Comments: 0

Ever since the turn of the millennium, researchers have been warning that wires and interconnects will have issues. Electron crashes were reported as early as 2001, and electromigration is rising to the forefront of problems at advanced nodes. The result? Chipmakers are looking at thicker wires for the first time as a way of dealing with resistance and capacitance issues. While this makes se... » read more

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