tag: Mentor Graphics

Blog Review: Aug. 21
By Ed Sperling - 21 Aug, 2013 - Comments: 0

By Ed Sperling Mentor’s Michael Ford recalls the worst meetings in the world—ones that involve materials in the manufacturing process. Unfortunately there were a lot of them, so they were more like working in a recurring nightmare. Paging Freddie Krueger. Synopsys’ Karen Bartleson talks with Angisys CEO Anupam Bakshi about why EDA companies need to collaborate, and what’s the risk ... » read more

The Week In Review: Aug. 16
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003, will become executive chairman of the board of directors. Dickerson was the CEO of Varian, which Applied Materials acquired in 2011. Synopsys introduced a Dolby decoder for its ARC process... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

A Study Of Model-Based Etch Bias Retarget For OPC
By Various Writers - 15 Aug, 2013 - Comments: 0

Model-based optical proximity correction is usually used to compensate for the pattern distortion during the microlithography process. Currently, almost all the lithography effects, such as the proximity effects from the limited NA, the 3D mask effects due to the shrinking critical dimension, the photo resist effects, and some other well known physical process, can all be well considered into m... » read more

I Just Want Closure!
By Jean-Marie Brunet - 15 Aug, 2013 - Comments: 0

By Jean-Marie Brunet We all know it by now, but let’s say it one more time for the cameras—the level of complexity of closure at 20 nm and below is considerably higher than for any previous nodes. While the migration of manufacturing requirements into design started with a few suggested activities at 65 nm, such as recommended rules compliance, lithography checks, and critical area analysi... » read more

Can Mask Data Prep Tools Manage Data Glut?
By Ann Mutschler - 15 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler The trend to reduce critical dimension sizes has in turn increased design file sizes, especially with the addition of optical proximity correction (OPC) steps. This extra data translates to a bigger burden to be processed downstream in the flow on the way to the mask writer. At 28nm, design post-OPC data files sizes reach hundreds of gigabytes. With 20nm and below ... » read more

Blog Review: Aug. 14
By Ed Sperling - 14 Aug, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang unveils the fastest USB ever. The seat belt is extra. Mentor’s Nazita Saye sees the light—well, at least a refracted version of it—through the lens of a plastic bottle. This one is a real energy saver for the money, even if you have to forfeit the recycling fee. Check out the link. Cadence’s Brian Fuller takes a sledgehammer to the semicond... » read more

Power Grid Analysis
By Christen Decoin - 08 Aug, 2013 - Comments: 1

By Christen Decoin With increasing design size at each technology node, power grid analysis (PGA) has been stretching established software capacity and performance for some time. At 32/28nm, capacity and performance issues finally presented significant barriers to achieving signoff. In this article, we explore existing approaches that EDA vendors have been trying to leverage to work around ... » read more

User Defined Fault Models
By Various Writers - 08 Aug, 2013 - Comments: 0

This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. To achieve today's quality and defect-per-million (DPM) goals, high-quality testing must achieve very high defect coverage. Testing today typically consists of generating test patterns based on multiple fault m... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate app... » read more

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