tag: Mentor

A New Dimension Of Complexity For IC Design
By Ann Mutschler - 27 Jan, 2022 - Comments: 0

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is used to validate a design’s timing performance by checking all possible paths for timing violations. STA issues began popping up particularly with the introduction of hybrid bonding, a bumpless p... » read more

Growth Spurred By Negatives
By Brian Bailey - 27 Jan, 2022 - Comments: 0

The success and health of the semiconductor industry is driven by the insatiable appetite for increasingly complex devices that impact every aspect of our lives. The number of design starts for the chips used in those devices drives the EDA industry. But at no point in history have there been as many market segments driving innovation as there are today. Moreover, there is no indication this... » read more

Greener Design Verification
By Brian Bailey - 27 Jan, 2022 - Comments: 0

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, or power consumption. Admittedly, one is a per unit cost while the other is a development cost, but could the industry be doing more to make development greener? It can take days for regression... » read more

Dependable Verification Is The Foundation ICs Require
By Pirzad Motafram - 27 Jan, 2022 - Comments: 0

As our world becomes increasingly high-tech, it is easy to lose sight of the little things that make all of our fancy gadgets achieve optimal performance. The one thread that enables you to get all of the benefits of a new laptop, tablet, smartphone, or your automobile’s digital dashboard and connects the components that ensure best performance is the integrated circuit (IC). For as breath... » read more

Veloce Coverage App And Veloce Assertion App Deliver Unified Coverage Methodology
By Siemens EDA - 26 Jan, 2022 - Comments: 0

The interoperability of the Veloce Coverage app and the Veloce Assertion app with other verification engines (simulation and formal) enables merging coverage collected by each engine and provides a cohesive coverage closure report and analysis flow. It enables the verification team and product-level management to make important decisions such as coverage closure sign-off, test quality analysis ... » read more

Blog Review: Jan. 26
By Jesse Allen - 26 Jan, 2022 - Comments: 0

Arm's Mark Inskip shares how the Morello prototype architecture, aimed at improving the security of hardware, was developed, from the creation of the prototype architecture specification, followed by the design and implementation of a new CPU, through to the development of a new SoC, hardware platform, development tools, toolchains, and software. Cadence's Paul McLellan looks at how the RISC... » read more

Photomask Challenges At 3nm And Beyond
By Mark LaPedus - 25 Jan, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 21 Jan, 2022 - Comments: 0

Fabs Intel has announced plans for an initial investment of more than $20 billion in the construction of two new leading-edge fabs in Ohio. Planning for the first two factories will start immediately, with construction expected to begin late in 2022. Production is expected to come online in 2025. As part of the announcement, Air Products, Applied Materials, Lam Research and Ultra Clean Technol... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Jan, 2022 - Comments: 0

Tools & design EDA industry revenue increased 7.1% year-over-year from $2.95 billion to $3.46 billion in Q3 2021, according to the ESD Alliance. "Geographically, all regions reported double-digit growth, with product categories CAE, Printed Circuit Board and Multi-Chip Module, SIP, and Services also showing double-digit growth," said Walden C. Rhines, Executive Sponsor of the SEMI Electron... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 21 Jan, 2022 - Comments: 0

Security Arm shipped a prototype CHERI-enabled Morello processor, SoC, and board, the first products coming from the security Morello research program that aims to make more secure hardware that will block certain common attacks. The first board prototypes are going to testing teams at Google, Microsoft, and other major stakeholders and partners across the industry and academia.  The UKRI (UK... » read more

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