tag: metrology

Advanced Modeling In FTIR Offers New Applications For HVM
By Benoit Ravot - 09 Nov, 2021 - Comments: 0

In the leading high-volume manufacturing (HVM) process flows, materials-enabled scaling has increased inline applications for compositional metrology. A previous blog discussed how Fourier transform infrared (FTIR) spectroscopy was used for inline composition measurements. These measurements informed advanced process control for the wafer-level processing of selectively etched 3D NAND wordli... » read more

Industrial Radiography — CT Scanning for Metrology Applications
By CyberOptics - 09 Nov, 2021 - Comments: 0

Xray technology, more specifically computed tomography (CT), has been adapted for use as an instrument of industrial metrology. Early adopters have quickly recognized the benefits of internal and external nondestructive testing for 3D defect detection and geometric analysis, while those considering adoption may be uncertain how to implement the technology effectively. This study was conducted t... » read more

The Everything New Syndrome
By Ed Sperling - 12 Oct, 2021 - Comments: 0

Technology is all about the latest features, the fastest processing, with the lowest power. While that sounds great in marketing pitch, any or all of those factors don't necessarily equate to a better product or long-term user satisfaction. There's a reason semiconductor companies are conservative by nature. They want to know that when they spend tens or hundreds of millions of dollars on a ... » read more

Probe assisted localized doping of aluminum into silicon substrates
By Technical Paper Link - 11 Oct, 2021 - Comments: 0

Abstract "This paper discusses the development of a rapid, large-scale integration of deterministic dopant placement technique for encoding information in physical structures at the nanoscale. The doped structures inherit identical and customizable radiofrequency (RF) electronic signature, which could be leveraged into an identification feature unique to the tag item. This will allow any manuf... » read more

Growing Challenges With Wafer Bump Inspection
By Ed Sperling - 11 Oct, 2021 - Comments: 1

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

High-NA EUVL: the next major step in lithography
By Technical Paper Link - 05 Oct, 2021 - Comments: 0

"In the course of 2025, we expect to see the introduction of the first high-NA extreme ultraviolet (EUV) lithography equipment in high-volume manufacturing environments. These next-generation lithography systems will be key to advance Moore’s Law towards the logic 2nm technology generation and beyond. In this article, imec scientists and engineers involved in preparing this major engine... » read more

Reducing Rework In CMP: An Enhanced Machine Learning-Based Hybrid Metrology Approach
By Vamsi Velidandla - 10 Aug, 2021 - Comments: 0

By Vamsi Velidandla, John Hauck, Zhuo Chen, Joshua Frederick, and Zhihui Jiao The semiconductor industry is constantly marching toward thinner films and complex geometries with smaller dimensions, as well as newer materials. The number of chemical mechanical planarization (CMP) steps has increased and, with it, a greater need for within-wafer uniformity and wafer-to-wafer control of the thin... » read more

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Reliability Costs Becoming Harder To Track
By Ed Sperling And Susan Rambo - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

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