tag: Northwestern University

Increasing AI Energy Efficiency With Compute In Memory
By Katherine Derbyshire - 16 Nov, 2023 - Comments: 0

Skyrocketing AI compute workloads and fixed power budgets are forcing chip and system architects to take a much harder look at compute in memory (CIM), which until recently was considered little more than a science project. CIM solves two problems. First, it takes more energy to move data back and forth between memory and processor than to actually process it. And second, there is so much da... » read more

Chip Industry’s Technical Paper Roundup: October 9
By Liz Allan - 09 Oct, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=153 /] More Reading Technical Paper Library home » read more

VCMA-Controlled MTJ Devices For Probabilistic Computing Applications
By Technical Paper Link - 03 Oct, 2023 - Comments: 0

A technical paper titled “Probabilistic computing with voltage-controlled dynamics in magnetic tunnel junctions” was published by researchers at Northwestern University, University of Messina, Western Digital Corporation, and Universitat Jaume I. Abstract: "Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by convent... » read more

Chip Industry Technical Paper Roundup: August 15
By Liz Allan - 15 Aug, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

New & Faster Single-Crystalline Oxide Thin Films (Max Planck, Cambridge, U of Penn.)
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “Li iontronics in single-crystalline T-Nb2O5 thin films with vertical ionic transport channels” was published by researchers at Max Planck Institute of Microstructure Physics, University of Cambridge, University of Pennsylvania, Gumi Electronics and Information Technology Research Institute, Northwestern University, and ALBA Synchrotron Light Source. Abstract: "Th... » read more

Research Bits: Aug. 7
By Jesse Allen - 07 Aug, 2023 - Comments: 0

Stretchy semiconductors Researchers from Pennsylvania State University, University of Houston, Southeast University, and Northwestern University are working towards fully flexible electronics. “Such technology requires stretchy elastic semiconductors, the core material needed to enable integrated circuits that are critical to the technology enabling our computers, phones and so much more,... » read more

Chip Industry’s Technical Paper Roundup: July 12
By Liz Allan - 12 Jul, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=117 /] (more…) » read more

How Voltage-Controlled MRAM Devices Can Be Used To Create Unique Fingerprints Of Microelectronic Chips
By Technical Paper Link - 08 Jul, 2023 - Comments: 0

A technical paper titled "Reconfigurable Physically Unclonable Functions Based on Nanoscale Voltage-Controlled Magnetic Tunnel Junctions" was published by researchers at Northwestern University, Western Digital Corporation, Fe Research Inc., and University of Messina. Abstract: "With the fast growth of the number of electronic devices on the internet of things (IoT), hardware-based securi... » read more

Chip Industry’s Technical Paper Roundup: Mar. 21
By Linda Christensen - 21 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=88 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A new technical paper titled "WARDen: Specializing Cache Coherence for High-Level Parallel Languages" was published by researchers at Northwestern University and Carnegie Mellon University. Abstract: "High-level parallel languages (HLPLs) make it easier to write correct parallel programs. Disciplined memory usage in these languages enables new optimizations for hardware bottlenecks, such ... » read more

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