tag: patterning

BEOL Barricades Ahead
By David Fried - 15 Dec, 2016 - Comments: 0

Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. Among the questions posed to panelists: What is BEOL? Where does it begin and end? Are there fundamental limits to interconnect processes? How much longer can we continue to use current interconnect processes and ... » read more

Sub-Lithographic Patterning Via Tilted Ion Implantation For Scaling Beyond The 7nm Technology Node
By Technical Paper Link - 10 Nov, 2016 - Comments: 0

Tilted ion implantation (TII) can be used in conjunction with pre-existing masking features on the surface of a substrate to form features with smaller dimensions and smaller pitch. In this paper, the resolution limit of this sub-lithographic patterning approach is examined via experiments as well as Monte Carlo process simulations. TII is shown to be capable of defining features with size belo... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

Interconnect Challenges Rising
By Mark LaPedus - 27 Jun, 2016 - Comments: 1

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

One-On-One: Dave Hemker
By Ed Sperling - 19 May, 2016 - Comments: 0

Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

3D Construction Ahead
By Michael Watts - 17 Mar, 2016 - Comments: 0

One of the interesting features of Photonics West is that it covers the full spectrum, from academic research to industrial research to new products in the commercial exhibits. This range of interrelated ideas was on show in 3D fabrication. At one extreme, the latest research in scanning multi-spot three-photon patterning showed 3D structures 100μm thick with 50nm features. Researchers als... » read more

5nm Fab Challenges
By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Patterning Interconnects At 10nm And Below
By Applied Materials - 20 Aug, 2015 - Comments: 0

By Connie Duncan Chip manufacturers today build billions of transistors on a chip, delivering incredible computing power to consumers. What often gets overlooked is how hard it’s getting to create the many miles of ultra-thin copper wiring used to connect each of the transistors. Patterning these electrical pathways is becoming increasingly challenging as they grow denser and finer, and any ... » read more

Fab Issues At 7nm And 5nm
By Mark LaPedus - 23 Jul, 2015 - Comments: 2

The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors. They're not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies f... » read more

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