tag: PCIe

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong
By Mondeep Thiara - 17 Jan, 2019 - Comments: 0

First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

PCIe In High-Performance FPGAs
By Vatsal Choksi - 26 Jul, 2018 - Comments: 0

In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, what are the factors that can assure such performance and speed? The value and success of today’s high performance computing applications in the areas of DNA Sequencing, High Frequency Trading (HFT) and Encryption/Decryption are predicated upon how fast data can be t... » read more

Software-Defined Test And Measurement
By Jeff Dorsch - 07 May, 2018 - Comments: 0

Software-defined radios, instrumentation and test are ramping up alongside a flood of new technologies related to assisted and autonomous vehicles, 5G, and military/aerospace electronics, breathing new life and significant change into the test and measurement market. Software-defined test adds flexibility in markets where the products and protocols are evolving or still being defined, and wh... » read more

Blog Review: April 4
By Jesse Allen - 04 Apr, 2018 - Comments: 0

Synopsys' Richard Solomon explains PCIe's upstream and downstream component naming and why understanding the perspective is key. Mentor's Cristian Filip dives into frequency domain analysis for high data rate SerDes links and the movement toward a simpler way of channel characterization. Cadence's Paul McLellan takes a look at the history of the RISC processors and the death of microcode ... » read more

32GT/s PCI Express Design Considerations
By Rita Horner - 08 Mar, 2018 - Comments: 0

Today’s networking and rapidly emerging artificial intelligence (AI) applications are requiring more bandwidth in accelerators and GPUs, as well as faster interconnects to transmit and receive greater amounts of data. Towards the middle of 2017 the PCI-SIG industry consortium announced its latest specification, PCIe 5.0, which raised the data rate from 16GT/s to 32GT/s and doubled the link... » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces
By Cadence - 07 Feb, 2018 - Comments: 0

As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Memory Test Challenges, Opportunities
By Jeff Dorsch - 18 Oct, 2017 - Comments: 0

The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

Targeting And Tailoring eFPGAs
By Ed Sperling - 17 Oct, 2017 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

CCIX – What And Why?
By Richard Solomon - 14 Sep, 2017 - Comments: 0

There are two significant issues with today’s I/O interconnects: high speed storage and networking applications need more bandwidth than currently available technologies provide, and co-processing/acceleration functions need cache coherency for faster access to memory in heterogeneous multi-processor systems. These requirements are driving the development of a new specification called Cache C... » read more

The Week In Review: IoT
By Jeff Dorsch - 25 Aug, 2017 - Comments: 0

Deals Advanced Semiconductor Engineering was selected by zGlue as its strategic manufacturing partner. The ASE Group will make the zGlue Integrated Platform, which is said to enable customization for consumer and industrial IoT markets. The ZiP integrates hardware and software in a modular 3DIC-based platform. ASE will assemble zGlue-certified chiplets for connecting through zGlue Smart Fabric... » read more

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