2D Semiconductors Make Progress, But So Does Silicon

By Katherine Derbyshire - 30 Oct, 2024 - Comments: 1

Semiconductor industry researchers have been anticipating the need for better transistor channel materials to replace silicon for a long time, but silicon devices have continued to improve enough to postpone that change. Silicon continues to provide an unmatched combination of device performance, manufacturability, and cost effectiveness. In recent years, though, the “end of silicon” cha... » read more

In-Product BTI Aging Sensor For Reliability Screening And Early Detection Of Material At Risk

By PDF Solutions - 09 Jan, 2024 - Comments: 0

We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging a... » read more

Will CFETs Help The Industry Go Vertical?

By Katherine Derbyshire - 15 Jun, 2023 - Comments: 0

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up. Today, this is much harder for several reasons: • Short channel effects limit gate-length scaling; • Parasitic effects limit device density, and • Metal resistance limits metal pitch. So r... » read more

FD-SOI Strains For The Future

By Katherine Derbyshire - 11 Jul, 2016 - Comments: 0

One of the challenges facing supporters of FD-SOI is the need to provide a pathway to improved performance. While FD-SOI wafers offer some significant advantages over bulk silicon wafers, performance enhancements like strain and alternative channel materials are more difficult to implement in the thin SOI environment. On the other hand, once a fab is willing to incorporate layer transfer techni... » read more

Reliability After Planar Silicon

By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

Next Channel Materials?

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

Re-Engineering The FinFET

By Mark LaPedus - 13 Nov, 2014 - Comments: 0

The semiconductor industry is still in the early stages of the [getkc id="185" kc_name="finFET"] era, but the [getkc id="26" kc_name="transistor"] technology already is undergoing a dramatic change. The fins themselves are getting a makeover. In the first-generation finFETs, the fins were relatively short and tapered. In the next wave, the fins are expected to get taller, thinner and more re... » read more

Ion Implanter Market Heats Up

By Mark LaPedus - 14 Aug, 2014 - Comments: 0

The ion implanter market has been a stable, if not a sleepy, business. The last big event took place in 2011, when Applied Materials re-entered the ion implanter market by acquiring Varian, the world’s leading supplier of these tools. The acquisition gave Applied Materials a commanding 80% share of the implanter business, with the other players fighting for the crumbs. But after year... » read more

Many Stresses Impact TSVs

By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

It’s A Materials World

By Mark LaPedus - 15 Aug, 2013 - Comments: 0

By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?