Chip Industry Technical Paper Roundup: Apr. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=419 /] Find more semiconductor research papers here. » read more

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)


A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

Chip Industry’s Technical Paper Roundup: July 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=118 /] (more…) » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR


A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Chip Industry’s Technical Paper Roundup: June 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=109 /] Further Reading Technical Paper Home » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)


A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

Chip Industry’s Technical Paper Roundup: May 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=103 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Recent Developments in Neuromorphic Computing, Focusing on Hardware Design and Reliability


A new technical paper titled "Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies" was published by researchers at Univ. Lyon, Ecole Centrale de Lyon, Univ. Grenoble Alpes, Hewlett Packard Labs, CEA-LETI, and Politecnico di Torino. Abstract "The field of neuromorphic computing has been rapidly evolving in recent years, with an incre... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures


A new technical paper titled "Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures" was published by researchers at National Tsing-Hua University, Politecnico di Torino, University of Rome Tor Vergata, and University of Twente. Abstract "Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Tow... » read more

← Older posts