tag: PPA

Tape Out On Time With Demand Signoff DRC In P&R
By Siemens EDA - 28 Jul, 2021 - Comments: 0

Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Best 112G SerDes IP Architecture
By Manu Verma - 08 Jul, 2021 - Comments: 0

Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

Cell Library Verification Using Symbolic Simulation
By Hari Sathianathan - 07 Jul, 2021 - Comments: 0

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

IP Solutions For A Data-Centric World
By Cadence - 23 Jun, 2021 - Comments: 0

We’re in an era of sizeable growth in data and compute demand, along with increasing global data traffic. As a result, high-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, hi... » read more

AI Testing: Pushing Beyond DFT Architectures
By Rahul Singhal - 27 May, 2021 - Comments: 0

Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and test methodologies. With thousands of repeated... » read more

Hyperconnectivity, Hyperscale Computing, And Moving Edges
By Frank Schirrmeister - 27 May, 2021 - Comments: 0

As described in “The Four Pillars of Hyperscale Computing” last year, the four core components that development teams consider for data centers are computing, storage, memory, and networking. Over the previous decade, requirements for programmability have fundamentally changed data centers. Just over a decade ago, in 2010, virtual machines would compute user workloads on CPU-centric archite... » read more

Addressing IC Hyperconvergence Design Challenges
By Aveek Sarkar - 11 Mar, 2021 - Comments: 0

Recently in an article titled “A Renaissance for Semiconductors,” my colleague Michael Sanie highlighted some of the trends that are driving next-generation product development. He detailed how designs targeting new applications are innovating through a combination of advanced process node technologies and heterogeneous integration of stacked die/3D/2.5D systems. Additionally, advanced vert... » read more

Know Your Own Power, Early And Accurately
By Taruna Reddy - 11 Feb, 2021 - Comments: 0

By Taruna Reddy and Vin Liao Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated p... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Fast, Low-Power Inferencing
By Russell Klein - 10 Dec, 2020 - Comments: 1

Power and performance are often thought of as opposing goals, opposite sides of the same coin if you will. A system can be run really fast, but it will burn a lot of power. Ease up on the accelerator and power consumption goes down, but so does performance. Optimizing for both power and performance is challenging. Inferencing algorithms for Convolutional Neural Networks (CNN) are compute int... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy