tag: process modeling

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

3D NAND Virtual Process Troubleshooting And Investigation
By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more

BEOL Integration For The 1.5nm Node And Beyond
By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

Accelerating Semiconductor Process Development Using Virtual Design Of Experiments
By Qingpeng Wang - 17 Mar, 2022 - Comments: 0

Design of Experiments (DOE) are a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect on final device performance. A well-designed DOE can help an engineer achieve a targeted semiconductor device performance using a limited number of experimental wafer runs. However, in se... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization
By Taeyon (TY) Oh - 20 Jan, 2022 - Comments: 0

Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

Understanding Electrical Line Resistance At Advanced Semiconductor Nodes
By Sandy Wen - 16 Dec, 2021 - Comments: 0

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by grain boundary effects and surface scattering. Consequently, resistivity varies throughout a line, and resistance extraction needs to account for these secondary phenome... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance
By Yu De Chen - 21 Oct, 2021 - Comments: 0

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

Using Virtual Process Libraries To Improve Semiconductor Manufacturing
By Jeonghoon (James) Kim - 17 Jun, 2021 - Comments: 0

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly a... » read more

Improving Your Understanding Of Advanced Inertial MEMS Design
By Chris Welham - 27 Apr, 2021 - Comments: 0

Micro-electrical-mechanical systems (MEMS) based inertial sensors are used measure acceleration and rotation rate. These sensors are integrated into units to measure motion, direction, acceleration or position, and can be found in a wide range of applications including smart phones, consumer electronics, medical devices, transportation systems, oil/gas exploration, military, aeronautical and sp... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy