tag: process modeling

BEOL Integration For The 1.5nm Node And Beyond
By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

Accelerating Semiconductor Process Development Using Virtual Design Of Experiments
By Qingpeng Wang - 17 Mar, 2022 - Comments: 0

Design of Experiments (DOE) are a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect on final device performance. A well-designed DOE can help an engineer achieve a targeted semiconductor device performance using a limited number of experimental wafer runs. However, in se... » read more

The Effect Of Pattern Loading On BEOL Yield And Reliability During Chemical Mechanical Planarization
By Taeyon (TY) Oh - 20 Jan, 2022 - Comments: 0

Chemical mechanical planarization (CMP) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, and to optimize the device topology prior to the next processing step. Unfortunately, the surface of a semiconductor device is not uniform after CMP, due to different re... » read more

Understanding Electrical Line Resistance At Advanced Semiconductor Nodes
By Sandy Wen - 16 Dec, 2021 - Comments: 0

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by grain boundary effects and surface scattering. Consequently, resistivity varies throughout a line, and resistance extraction needs to account for these secondary phenome... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance
By Yu De Chen - 21 Oct, 2021 - Comments: 0

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

Using Virtual Process Libraries To Improve Semiconductor Manufacturing
By Jeonghoon (James) Kim - 17 Jun, 2021 - Comments: 0

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly a... » read more

Improving Your Understanding Of Advanced Inertial MEMS Design
By Chris Welham - 27 Apr, 2021 - Comments: 0

Micro-electrical-mechanical systems (MEMS) based inertial sensors are used measure acceleration and rotation rate. These sensors are integrated into units to measure motion, direction, acceleration or position, and can be found in a wide range of applications including smart phones, consumer electronics, medical devices, transportation systems, oil/gas exploration, military, aeronautical and sp... » read more

Overcoming Challenges In Next-Generation SRAM Cell Architectures
By Benjamin Vincent - 18 Mar, 2021 - Comments: 0

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each other in order to perform logic storage and other functions. The size of the 6T (6 Transistors) SRAM cell has shrunk steadily over the past decades, thanks to Moore’s Law and the size reduction of t... » read more

The Future Of FinFETs At 5nm And Beyond
By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more

An Introduction To Virtual Semiconductor Process Evaluation
By Jeonghoon (James) Kim - 21 Jan, 2021 - Comments: 0

Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force... » read more

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