tag: process modeling

Accelerating Dry Etch Processes During Feature Dependent Etch
By Timothy Yang - 23 Nov, 2020 - Comments: 0

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (figure 1). This has an impact on etch results, since the etch rate at any point on the wafer will vary depending on the solid angle visible to the bulk chamber and the ion flux for that angular range. These non-uniform and feature dependent e... » read more

Micro Loading And Its Impact On Device Performance
By Qingpeng Wang - 02 Nov, 2020 - Comments: 0

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

Winning The Global Race For Semiconductor Technology With Virtual Fabrication
By David Fried - 22 Oct, 2020 - Comments: 0

Semiconductor process development is no easy task, with each generation of devices more difficult and expensive to create. Traditional cycles of build-and-test development are becoming obsolete, since they are too expensive and time-consuming for the most advanced processes. The high cost of process development Most chip designers developing new products rely on existing manufacturing process... » read more

Building Predictive And Accurate 3D Process Models
By Pradeep Nanja - 21 Sep, 2020 - Comments: 0

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model is to ensure that the model is calibrated. Having a calibrated model is important, since it provides assurance to the process integrators and engineers that the model will refle... » read more

Process Model Calibration: Building Predictive And Accurate 3D Process Models
By Coventor - 16 Sep, 2020 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Process Model Calibration: Building Predictive and Accurate 3D Process Models
By Coventor - 20 Aug, 2020 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Semiconductor Memory Evolution And Current Challenges
By Michael Hargrove - 16 Jul, 2020 - Comments: 0

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. The evolution of computer memory since that time has included numerous magnetic memory systems, such as magnetic drum memory, magnetic core memory, magnetic tape drive, and magnetic bubble memory. Since the 19... » read more

An Introduction To Semiconductor Process Modeling
By Jeonghoon (James) Kim - 20 Dec, 2019 - Comments: 0

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort. Basic concept The easiest way to predict a process result is to model its b... » read more

Advanced Patterning Techniques For 3D NAND Devices
By Yu De Chen - 15 Aug, 2019 - Comments: 0

By Yu De Chen and Jacky Huang Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At th... » read more

Creating Higher Density 3D NAND Structures
By Timothy Yang - 21 Feb, 2019 - Comments: 0

3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND structures, even when fabricated on later generation technology nodes. The methods used to increase storage capacity come with potentially significant tradeoffs in memory storage, structural sta... » read more

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