2019 – The Year Of The “Dynamic Duo” Of Emulation and Prototyping

By Frank Schirrmeister - 30 Jan, 2020 - Comments: 0

In technology, we are always trying to figure out when we have reached critical mass, have crossed the chasm, or even can be considered mainstream. We all have seen the adoption curves for consumer products. In design and verification technology, a distinct B2B setting with fewer end customers than in the B2C domain, the situation seems to be even worse as there is no “one flow” to design a... » read more

Evaluating NVMe SSD Multi-Gigabit Performance

By Igor Gorokhov - 30 Jan, 2020 - Comments: 0

The multi-channel parallelism and low-latency access of NAND flash technology have made Non-Volatile Memory express (NVMe) based SSDs very popular within the main segments of the data storage market, including not only the consumer electronics sector but also data center processing and acceleration services, where the key role is played by specialized FPGA-based hardware for application-specifi... » read more

Using PCIe Real World Interface For High-Speed Hybrid Prototyping

By Synopsys - 25 Nov, 2019 - Comments: 0

This white paper highlights a novel approach to hybrid prototyping using a PCIe interface between the HAPS FPGA-based prototyping and the Virtualizer virtual prototyping. The use of PCIe real world interface helps to deliver a prototyping system, running fast enough to enable embedded software development and hardware-software co-validation in the shortest possible time. The hybrid prototyping ... » read more

Which Verification Engine When

By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Joint Optimization Of Hardware And Compiler

By Synopsys - 01 May, 2019 - Comments: 0

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking. This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning framework/compile... » read more

Designing Networking Chips

By Ed Sperling - 07 Feb, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

FPGA Graduates To First-Tier Status

By Ed Sperling - 06 Dec, 2018 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to talk about fundamental shifts in compute architectures and why AI, machine learning and various vertical applications are driving demand for discrete and embedded FPGAs. SE: What’s changing in the FPGA market? Blake: Our big focus is developing the next-generation architecture. We started this projec... » read more

New 5G Hurdles

By Ed Sperling - 01 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018

By Frank Schirrmeister - 26 Apr, 2018 - Comments: 0

Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

The Week In Review: Design

By Jesse Allen - 20 Apr, 2018 - Comments: 0

M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

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