tag: RDL

Defect Challenges Growing In Advanced Packaging
By Mark LaPedus - 08 Oct, 2018 - Comments: 0

The current defect inspection systems for packaging are running out of steam for the latest advanced packages, prompting the need for new tools in the market. In response, several vendors are rolling out new defect inspection systems for use in various advanced packages, such as 2.5D/3D technologies and fan-out. The new defect inspection systems are more capable than the previous tools, but ... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science
By Kim Yess - 10 Sep, 2018 - Comments: 0

Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

Return Of The Organic Interposer
By Ed Sperling - 06 Aug, 2018 - Comments: 2

Organic interposers are resurfacing as an option in advanced packaging, several years after they were first proposed as a means of reducing costs in 2.5D multi-die configurations. There are several reasons why there is a renewed interest in this technology: More companies are pushing up against the limits of Moore's Law, where the cost of continuing to shrinking features is exorbitant. ... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications
By STATS ChipPAC - 11 Dec, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Going Vertical?
By Debra Vogler - 15 Jun, 2017 - Comments: 0

The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

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