tag: reliability

How To Make Autonomous Vehicles Reliable
By Ann Mutschler - 11 Sep, 2017 - Comments: 1

The number of unknowns in automotive chips, subsystems and entire vehicles is growing as higher levels of driver assistance are deployed, sparking new concerns and approaches about how to improve reliability of these systems. Advanced Driver Assistance Systems (ADAS) will need to detect objects, animals and people, and they will be used for parking assistance, night vision and collision avoi... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

The Rising Value Of Data
By Ed Sperling - 09 Aug, 2017 - Comments: 0

The volume of data being generated by a spectrum of devices continues to skyrocket. Now the question is what can be done with that data. By Cisco's estimates, traffic on the Internet will be 3.3 zetabytes per year by 2021, up from 1.2 zetabytes in 2016. And if that isn't enough, the flow of data isn't consistent. Traffic on the busiest 60-minute period in a day increased 51% in 2016, compare... » read more

Who’s Responsible For Transistor Aging Models?
By Ann Mutschler - 13 Jul, 2017 - Comments: 0

While there are a number of ways to go about reliability and transistor aging analysis, it is all in large part dependent on fabs and foundries to provide the aging models. The situation is also not entirely clear in the semiconductor ecosystem because the classic over-the-wall mentality between design and manufacturing still exists. And unfortunately this wall is bi-directional. Not only... » read more

Transistor Aging Intensifies At 10/7nm And Below
By Ann Mutschler - 13 Jul, 2017 - Comments: 0

Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below. Concepts like ‘infant mortality’ and 'bathtub curves' are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which... » read more

Chip Test Shifts Left
By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

Focus Shifts To System Quality
By Ed Sperling - 05 Jun, 2017 - Comments: 0

For the past decade, many semiconductor industry insiders predicted that software would take over the world and hardware would become commoditized. The pendulum seems to have stopped, and if anything, it is reversing course. Initial predictions were based on several advantages for software. First, software is easier to modify and patch. Second, universities turn out far more software develop... » read more

Autonomous Cars Drive New Software
By Ann Mutschler - 04 May, 2017 - Comments: 0

Autonomous driving and other advanced features will require much more sophisticated software than what is used in vehicles today. To make this all work will require complex algorithms as well as co-designed hardware, which can make real-time decisions to avoid accidents and adjust to changing road conditions. Automobiles already take advantage of sophisticated software executed by a variety ... » read more

Verification And The IoT
By Ed Sperling - 04 May, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

When Will It Be Done?
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Design teams have done remarkably well in getting chips out the door on time, despite growing complexity at each new node and an increase in the number of features and IP blocks that need to be integrated into designs. There has been plenty of grumbling, along with dire warnings about the future of Moore's Law and the impact of industry consolidation. The reality, though, is that the volume ... » read more

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