tag: Samsung

Week In Review, Manufacturing, Test
By Karen Heyman - 01 Jul, 2022 - Comments: 0

Samsung announced initial production of its 3nm process node, which uses a gate-all-around (nanosheet) transistor structure that the company calls Multi-Bridge-Channel FET (MBCFET). The first-generation 3nm process can reduce power consumption by up to 45% compared with a 5nm process, as well as improve performance by 23% and reduce area by 16%, according to the company. The second-generation 3... » read more

EDA Gaps At The Leading Edge
By Ed Sperling - 29 Jun, 2022 - Comments: 1

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 27 May, 2022 - Comments: 0

Broadcom announced it will acquire cloud computing and virtualization company VMware for about $61 billion in cash and stock, and assume $8 billion in VMware net debt. If all goes as planned, the Broadcom Software Group will rebrand and operate as VMware. “The combined solutions will enable customers, including leaders in all industry verticals, greater choice and flexibility to build, run, m... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 May, 2022 - Comments: 0

EnSilica listed on the London Stock Exchange's AIM market under the ticker ENSI. EnSilica designs mixed signal ASICs for system developers in the automotive, industrial, healthcare, and communications markets. It also has a portfolio of core IP covering cryptography, radar and communications systems. AIM is the LSE’s market for small and medium sized growth companies. "In connection with Admi... » read more

Standardizing Chiplet Interconnects
By John Koon - 23 May, 2022 - Comments: 0

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

Paving The Way To Chiplets
By Mark LaPedus - 25 Apr, 2022 - Comments: 2

The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

Photomask Shortages Grow At Mature Nodes
By Mark LaPedus - 21 Apr, 2022 - Comments: 2

A surge in demand for chips at mature nodes, coupled with aging photomask-making equipment at those geometries, are causing significant concern across the supply chain. These issues began to surface only recently, but they are particularly worrisome for photomasks, which are critical for chip production. Manufacturing capacity is especially tight for photomasks at 28nm and above, driving up ... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 15 Apr, 2022 - Comments: 0

Photonic Chips Go Big In Europe PhotonDelta, a collaborative end-to-end supply chain for the application of photonics chips, secured €1.1 billion in conditional funding for a six-year initiative. Investments from the Netherlands government and other organizations “will be used to build 200 startups, scale up production, create new applications for photonic chips, and develop infrastructure... » read more

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

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