tag: semiconductor packaging

Research on the Humidity Resistance Reliability of Different Packaging Structures
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "Packaging process is an indispensable part in the process of electronic components manufacturing, and its packaging quality directly affects the nominal power, reliability and other functions of the product in the subsequent application process. Through the research on the humidity resistance reliability of different packaging structures, C-Mount packaging structure, TO packaging str... » read more

Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation
By Technical Paper Link - 31 Oct, 2021 - Comments: 0

Abstract: "Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fi... » read more

Open Cavity Plastic Packaging
By Ed Sperling - 30 Sep, 2021 - Comments: 0

Rapid change in electronics is also causing rapid obsolescence. But in some markets, the systems are supposed to last for decades. Sam Sadri, senior process engineer at QP Technologies (formerly Quik-Pak), talks with Semiconductor Engineering about why it’s so important to use existing package footprints, what are the challenges in replacing the circuitry inside a package, and which markets a... » read more

Challenges With Chiplets And Packaging
By Mark LaPedus - 15 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

What Goes Wrong In Advanced Packages
By Ed Sperling - 24 Mar, 2021 - Comments: 1

Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

System-Level Packaging Tradeoffs
By Ann Mutschler - 30 Sep, 2020 - Comments: 0

Leading-edge applications such as artificial intelligence, machine learning, automotive, and 5G, all require high bandwidth, higher performance, lower power and lower latency. They also need to do this for the same or less money. The solution may be disaggregating the SoC onto multiple die in a package, bringing memory closer to processing elements and delivering faster turnaround time. But ... » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Hidden Soldier Joints Inspection: 4 Case Studies
By DELTA, a part of FORCE Technology - 07 May, 2019 - Comments: 0

IC packaging technologies are becoming smaller and thinner. Ball grid array (BGA) packages were introduced some years ago in order to save space on the PCB, and are now widely used. To overcome the resulting problems with using optical microscopy as an inspection tool, the endoscope found its way into quality engineering departments. To read more, click here. » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost
By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy