tag: Siemens EDA

Ensuring ESD Protection Verification With Industry-Standard Checks
By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

RISC-V Pushes Into The Mainstream
By Ed Sperling - 21 Dec, 2022 - Comments: 1

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

Speed Up Early Design Rule Exploration And Physical Verification
By Siemens EDA - 21 Dec, 2022 - Comments: 0

Ensuring that early-stage IC design physical verification actually enhances IC design and verification productivity means giving engineers the ability to focus on those errors that are both valid and critical in early-stage designs. The Calibre nmDRC Recon functionality provides selective DRC of early-stage designs that focuses on real, relevant errors, ignoring rule checks that generate meanin... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2022 - Comments: 0

Synopsys' Twan Korthorst explains how PDKs can help accelerate the photonic IC design process by offering building blocks such as several types of waveguides, passive devices like splitters, combiners, and filters, along with active devices such as phase shifters, detectors, semiconductor optical amplifiers, and lasers. Siemens EDA's Harry Foster examines IC and ASIC design trends, including... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

The March Toward Chiplets
By Ed Sperling and Karen Heyman - 15 Dec, 2022 - Comments: 0

The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

3D-IC Reliability Degrades With Increasing Temperature
By Ann Mutschler - 14 Dec, 2022 - Comments: 0

The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster checks out design and verification language adoption trends in FPGA projects, including testbench methodologies and assertion languages. Cadence's Veena Parthan finds that giving electric vehicle batteries a second life as energy storage devices can extend their useful life by 5 to 8 years, but a lack of standardization in EV batteries poses challenges. Synopsys... » read more

Variability Becoming More Problematic, More Diverse
By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

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