tag: Siemens

Week In Review: Design, Low Power
By Jesse Allen - 19 Jun, 2020 - Comments: 0

Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Blog Review: June 17
By Jesse Allen - 17 Jun, 2020 - Comments: 0

Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

Is Common Resistance Affecting Your Analog Design Reliability And Performance?
By Hossam Sarhan - 11 Jun, 2020 - Comments: 0

Integrated circuit (IC) design reliability has always been important and essential to market success. After all, if no one could count on your product to operate as designed, and for as long as intended, there wouldn’t be many buyers! However, given the increase in the types and complexity of design applications, coupled with the increasing technological challenge of manufacturing at advance... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

ESD Requirements Are Changing
By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

Using Calibre For Advanced IC Packaging Verification And Signoff
By Mentor, a Siemens Business - 10 Jun, 2020 - Comments: 0

As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

Blog Review: June 10
By Jesse Allen - 10 Jun, 2020 - Comments: 0

Cadence's Paul McLellan considers the issues around benchmarking neural networks running on different hardware and challenges in comparing designs. Mentor's Shivani Joshi points to a few of the different types of jitter and some key factors to review when trying to limit jitter. Synopsys' Fred Bals notes that while the National Vulnerability Database is a good source for information on public... » read more

Making Silicon Photonics Chips More Reliable
By Ed Sperling - 09 Jun, 2020 - Comments: 0

Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn't so simple. While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That's mostly due to the fact that Moore's Law scaling h... » read more

DAC 2020: Virtual And Different
By Ed Sperling - 08 Jun, 2020 - Comments: 0

Zhuo Li, group director at Cadence, and Harry Foster, chief scientist at Mentor, a Siemens Business, talk about the changes in content for this year's Design Automation Conference. » read more

Data Strategy Shifting Again In Cars
By Ann Mutschler - 04 Jun, 2020 - Comments: 0

Carmakers are modifying their data processing strategies to include more processing at or near the source of data, reducing the amount of data that needs to be moved around within a vehicle to both improve response time and free up compute resources. These moves are a world away from the initial idea that terabytes of streaming data would be processed in the cloud and sent back to the vehicl... » read more

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