tag: SoCs

Harness System-Level Data To Optimize Many-Core AI And ML Chips
By Siemens EDA - 10 Aug, 2021 - Comments: 0

The novel multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications are expected to deliver huge improvements in power efficiency. However, chip development teams and the customers for their devices face the growing complexity of hardware-software co-optimization, validation, and debug. In short, these SoCs are increasingly difficult to validate and... » read more

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats
By Siemens EDA - 04 Aug, 2021 - Comments: 0

SoC integrators know that a software-only chip security plan leaves devices open to attack. The more effective way to thwart hackers is to combat both digital and analog threats by incorporating security-focused hardware modules built into the core machine design. This paper describes sources of vulnerabilities to cyber attacks and what infrastructure is needed to secure against them. The So... » read more

Virtual Prototyping In SoC Development
By Christoph Sohrmann - 21 Jun, 2021 - Comments: 0

Modern semiconductor technologies enable manufacturers to pack more and more functions and memory into a single silicon die. While steadily advancing microintegration based on Moore’s Law just a few years ago mainly focused on increasing the clock frequency of integrated circuits (IC), today, it’s the design complexity and number of blocks that enable new IC functions. More and more logic b... » read more

The Case For FPGAs In Cars
By Bryon Moyer - 03 Jun, 2021 - Comments: 0

Field-programmable gate arrays (FPGAs) thrive in rapidly evolving new markets before being replaced by hard-wired ASICs, but in automotive that crossover is likely to happen significantly later than in the past. Historically, FPGAs have held temporary positions until volumes increased enough to cost-reduce the FPGAs out in favor of a hardened version. With automobiles, there are so many chan... » read more

Advanced Packaging For Improved Network Communications
By Amkor - 14 Apr, 2021 - Comments: 0

The global demand for data increases day-by-day. At the same time, the data transmission rate will increase to exceed 1 Terabits per second (Tbps) near the middle of this decade. To address this situation and provide a third alternative, engineers are increasingly looking into the chiplet approach with multiple smaller dies integrated in a single package. Only the logic portion that needs to... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Security In FPGAs And SoCs
By Ed Sperling - 23 Feb, 2021 - Comments: 0

Chip security is becoming a bigger problem across different markets, with different emerging standards and more sophisticated attacks. Jason Moore, senior director of engineering at Xilinx, talks with Semiconductor Engineering about current and future threats and what can be done about them. » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Exhaustive Verification of Reset Domain Crossings
By Synopsys - 08 Apr, 2020 - Comments: 0

It is difficult to imagine an aspect of semiconductor development more fundamental than reset. The ability to initialize the entire hardware design and clean all software running through a system-on-chip (SoC) is essential. Stating with a known state avoids propagation of signals with unknown values. Despite the best efforts at verification, lingering corner case bugs may put a system into a st... » read more

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