Thinner Channels With 2D Semiconductors

By Katherine Derbyshire - 21 Jun, 2021 - Comments: 0

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

Upturn Seen For Silicon Wafer Market

By Mark LaPedus - 19 Nov, 2020 - Comments: 0

After a downturn in 2019, the silicon wafer market is expected to rebound in 2020. 2021 looks even better for silicon wafers. Silicon wafers are a fundamental part of the semiconductor business. Every chipmaker needs to buy them in one size or another. Silicon wafer vendors produce and sell bare or raw silicon wafers to chipmakers, who in turn process them into chips. The silicon wafer ma... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

By Coventor - 17 Jun, 2020 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

ESD Requirements Are Changing

By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication

By Coventor - 01 Jun, 2020 - Comments: 0

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more

Design Of An Ultra-Low-Power Current Steering DAC In A Modern SOI technology

By Fraunhofer IIS/EAS - 13 May, 2020 - Comments: 0

Despite the tremendous advancement in innovations on digitizing and processing signals over the last century, real world signals are inevitably analog in nature. A digital-to-analog converter (DAC) serves in translating these digitized signals into different analog quantities like voltage, current or charges. We mainly focus on a Nyquist-rate current-steering digital- to-analog converte... » read more

Manufacturing Bits: Dec. 31

By Mark LaPedus - 31 Dec, 2019 - Comments: 0

GaN-on-SOI power semis At the recent IEEE International Electron Devices Meeting (IEDM), Imec and KU Leuven presented a paper on a gallium-nitride (GaN) on silicon-on-insulator (SOI) technology for use in developing GaN power devices. With GaN-on-SOI technology, researchers have developed a 200-volt GaN power semiconductor device with an integrated driver and fast switching performance. ... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options

By Coventor - 21 Nov, 2019 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. [1] The fabrication of a Complementary-Field Effect Transistor... » read more

Manufacturing Bits: April 23

By Mark LaPedus - 23 Apr, 2019 - Comments: 0

Sorting nuclei CERN and GSI Darmstadt have begun testing the first of two giant magnets that will serve as part of one of the largest and most complex accelerator facilities in the world. CERN, the European Organization for Nuclear Research, recently obtained two magnets from GSI. The two magnets weigh a total of 27 tons. About 60 more magnets will follow over the next five years. These ... » read more

Mixed Outlook For Silicon Wafer Biz

By Mark LaPedus - 21 Feb, 2019 - Comments: 0

After a period of record growth, the silicon wafer industry is off to a slow start in 2019 and facing a mixed outlook. Generally, 200mm silicon wafer supply remains tight. But demand for 300mm silicon wafers is cooling off in some segments, causing supply to move toward equilibrium after a period of shortages. On average, though, silicon wafer prices continue to rise despite the slowdown. ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: SOI