tag: stacked die

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

Different Economies Of Scale, And Lots Of Questions
By Ed Sperling - 12 Dec, 2013 - Comments: 0

Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair. The argument being presented is that economies of scale will still exist for those companies with pockets deep enough ... » read more

3D-IC Requires Expanded Power Grid Analysis
By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Counting Pennies
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm. With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistor... » read more

Tech Talk: 2.5D Stacked Die
By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

The Next Dimension
By Ed Sperling - 14 Nov, 2013 - Comments: 0

It’s hard to say definitively whether this is a trend or an aberration, but after what appears to have been a slam-dunk sprint to the finish line with finFETs some companies are re-evaluating their alternatives based upon return on investment. In place of perpetually shrinking features—and looming multipatterning at the next node—there is renewed interest in staying at 28nm with FDSOI,... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

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