tag: stacked die

Powerful Memories
By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

Follow The Investments
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Where is design heading over the next few years. The best way to tell that is to find out where the development dollars are going, and foundries and tools always precede actual designs. The foundries are starting to spend money—lots of it—on finFETs and 28nm. And while they’re talking about 2.5D and 3D, the money isn’t going there just yet. In fact, there are two different processes ... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Time To Revisit 2.5D And 3D
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

How Much Will That Chip Cost?
By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

Challenges In 3D Resists
By Katherine Derbyshire - 24 Mar, 2014 - Comments: 2

3D integration straddles the line between CMOS fabs and packaging and assembly houses. Depending on the structure being fabricated, the most appropriate process might be more “CMOS-like” or more “package-like.” For example, in CMOS fabs lithography means spin-on photoresist, exposed by a high precision stepper. Inherent in this approach is an assumption that the wafer surface is flat... » read more

Litho Is Out Of Sync
By Ed Sperling - 20 Mar, 2014 - Comments: 0

EUV’s repeated missed deadlines, and the slow-motion response by the rest of the industry to fill the void with alternatives, is having ripple effects in every facet and corner of the semiconductor industry. It’s making design harder and more expensive, introducing potential errors into the DFM flow, and greatly increasing the amount of time it takes to process wafers. It’s also adding a ... » read more

The Final Deadline For EUV
By Ed Sperling - 27 Feb, 2014 - Comments: 5

When TSMC disclosed this week—in a public forum—that its production EUV lithography test had failed in one of the early test runs due to a power source issue, there were very different reactions. EUV, after all, is an emotional issue with billions of dollars invested and lots of jobs riding on this technology. To begin with, there has been the usual spin control. The message essentially ... » read more

Evolution Vs. Revolution
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

In the electronic design automation industry changes to tools and flows are nearly always evolutionary. They hide as much change from the user as possible, allowing easier justification from an ROI perspective, and they raise far fewer objections from users, who don’t have to spend time learning how to use new technology or rethink tried and true approaches to problems. Revolution in chip ... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

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