tag: stacked die

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

Can We Ever Agree On Moore’s Law?
By Ed Sperling - 13 Feb, 2014 - Comments: 0

Nearly five decades after Moore’s Law was first introduced—the famous observation turns 50 next year—we’re still debating it. There are disagreements about whether it was an economic or technology statement. There are questions about whether it was really every 24 months or every 18 months—it was actually both. And there are questions about which companies it really applied to and who... » read more

Tech Talk: Power, Performance And Area In 2.5D
By Ed Sperling - 12 Feb, 2014 - Comments: 2

The cost will be comparable at first, but the only way to improve power, performance AND area at the same time will be with a different architectural approach. [youtube vid=XAbE7jpjuMA] » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 27 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As an industry we’ve got a pretty good grasp ... » read more

The Road Ahead for 2014: Semiconductors
By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

Different Economies Of Scale, And Lots Of Questions
By Ed Sperling - 12 Dec, 2013 - Comments: 0

Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair. The argument being presented is that economies of scale will still exist for those companies with pockets deep enough ... » read more

3D-IC Requires Expanded Power Grid Analysis
By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy