tag: stacked die

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Counting Pennies
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm. With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistor... » read more

Tech Talk: 2.5D Stacked Die
By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

The Next Dimension
By Ed Sperling - 14 Nov, 2013 - Comments: 0

It’s hard to say definitively whether this is a trend or an aberration, but after what appears to have been a slam-dunk sprint to the finish line with finFETs some companies are re-evaluating their alternatives based upon return on investment. In place of perpetually shrinking features—and looming multipatterning at the next node—there is renewed interest in staying at 28nm with FDSOI,... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

Temporary Bonding, Debonding Remains Challenging For TSV Adoption
By Jeff Chappell - 28 Oct, 2013 - Comments: 0

By Jeff Chappell One issue with the adoption of TSVs in 3D ICs in mainstream semiconductor applications revolves around the throughput of the temporary wafer bonding and debonding process. This doesn't necessarily equate to a roadblock, but work certainly remains to be done on this and related issues. On one hand, TSVs already are being used in the manufacturing of compound semiconductors ... » read more

TSVs: Welcome To The Era Of Probably Good Die
By Jeff Chappell - 21 Oct, 2013 - Comments: 0

Among the challenges of a widespread adoption of 3D ICs is how to test them, particularly when it comes to through-silicon vias (TSVs). While not necessarily presenting a roadblock, TSVs use in the mainstream will almost certainly change traditional test strategies. In fact for many chipmakers looking to stack their silicon, they may come to rely less on the traditional known good die (KGD) ... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

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