tag: stacked die

Standards Watch
By Ed Sperling - 17 Oct, 2013 - Comments: 0

This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing. The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standard... » read more

The Upside Of Through-Silicon Vias
By Katherine Derbyshire - 17 Oct, 2013 - Comments: 0

Through-silicon vias (TSVs) for 3D integration are superficially similar to damascene copper interconnects for integrated circuits. Both etch the via, into either silicon or a dielectric, line it with a barrier against copper diffusion, then deposit a seed layer prior to filling the via with copper using some form of aqueous deposition. In both processes, the integrity of the diffusion barrier ... » read more

Viable Choices Ahead
By Ed Sperling - 27 Sep, 2013 - Comments: 0

Two years ago—basically one process node back, wherever companies were on the Moore’s Law road map—there was confusion about what lies ahead and what is the best way to proceed. During that time, three very viable options have been proven to work. Some already are in silicon, while others are coming very soon. The first is the finFET. At the very leading edge of the road map, finFET... » read more

Time To Think
By Ed Sperling - 26 Sep, 2013 - Comments: 0

The semiconductor industry seems to be running place these days—maybe even sprinting in place. At the leading edge of design, companies are still looking at the ramifications of moving to finFETs. The move to a 20nm process with double patterning on 16/14nm finFETs, depending on the foundry, looks like a fairly safe bet for those companies with the volume and the resources to design and de... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Front End Comes To The Back End
By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

Experts At The Table: Process Technology Challenges
By Mark LaPedus - 13 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 23 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

Memory Architectures Undergo Changes
By Ed Sperling - 22 Aug, 2013 - Comments: 0

By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more

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