Temporary Bonding, Debonding Remains Challenging For TSV Adoption

By Jeff Chappell - 28 Oct, 2013 - Comments: 0

By Jeff Chappell One issue with the adoption of TSVs in 3D ICs in mainstream semiconductor applications revolves around the throughput of the temporary wafer bonding and debonding process. This doesn't necessarily equate to a roadblock, but work certainly remains to be done on this and related issues. On one hand, TSVs already are being used in the manufacturing of compound semiconductors ... » read more

TSVs: Welcome To The Era Of Probably Good Die

By Jeff Chappell - 21 Oct, 2013 - Comments: 0

Among the challenges of a widespread adoption of 3D ICs is how to test them, particularly when it comes to through-silicon vias (TSVs). While not necessarily presenting a roadblock, TSVs use in the mainstream will almost certainly change traditional test strategies. In fact for many chipmakers looking to stack their silicon, they may come to rely less on the traditional known good die (KGD) ... » read more

Experts At The Table: Debug

By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Standards Watch

By Ed Sperling - 17 Oct, 2013 - Comments: 0

This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing. The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standard... » read more

The Upside Of Through-Silicon Vias

By Katherine Derbyshire - 17 Oct, 2013 - Comments: 0

Through-silicon vias (TSVs) for 3D integration are superficially similar to damascene copper interconnects for integrated circuits. Both etch the via, into either silicon or a dielectric, line it with a barrier against copper diffusion, then deposit a seed layer prior to filling the via with copper using some form of aqueous deposition. In both processes, the integrity of the diffusion barrier ... » read more

Viable Choices Ahead

By Ed Sperling - 27 Sep, 2013 - Comments: 0

Two years ago—basically one process node back, wherever companies were on the Moore’s Law road map—there was confusion about what lies ahead and what is the best way to proceed. During that time, three very viable options have been proven to work. Some already are in silicon, while others are coming very soon. The first is the finFET. At the very leading edge of the road map, finFET... » read more

Time To Think

By Ed Sperling - 26 Sep, 2013 - Comments: 0

The semiconductor industry seems to be running place these days—maybe even sprinting in place. At the leading edge of design, companies are still looking at the ramifications of moving to finFETs. The move to a 20nm process with double patterning on 16/14nm finFETs, depending on the foundry, looks like a fairly safe bet for those companies with the volume and the resources to design and de... » read more

The Week In Review: Sept. 20

By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Front End Comes To The Back End

By Jeff Chappell - 19 Sep, 2013 - Comments: 0

By Jeff Chappell For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking. A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the... » read more

Experts At The Table: Process Technology Challenges

By Mark LaPedus - 13 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: stacked die