tag: STMicroelectronics

Week 49: Are We There Yet?
By Anne Cirkel - 15 May, 2015 - Comments: 0

When I was a little kid my parents would pack me and my sister into the car and drive to the Mediterranean for our summer camping vacation. It was quite a haul from our home on the west side of Germany near the border with Belgium to the south of France, and as is true of any long car trip, the last stretch was the hardest. After hours in the backseat, my sister and I would be craning our necks... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

The Next Generation Of Wearables
By Ernest Worthman - 07 May, 2015 - Comments: 0

As the wearable market begins to take root, so has the focus on ultra-low power design—with some unique headaches that are unique to wearables. To begin with, there is much attention being paid to this market because of the almost staggering predictions associated with it. While numbers vary greatly, IDC predicts as many as 126 million units will be shipping annually by 2019. The five-year... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Partly Sunny, With A Chance For Explosive Growth
By Mike Gianfagna - 23 Apr, 2015 - Comments: 0

I recently attended a session at the Mentor Graphics User Conference (User2User) in San Jose that dealt with the changing foundry landscape. The session was moderated by SemiWiki's Dan Nenni and included: • Giorgio Cesana, director of technology at STMicroelectronics • Jack Harding, co-founder, president & CEO of eSilicon • Lluis Paris, deputy director of worldwide IP alliances at ... » read more

Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools And Techniques
By Cadence - 22 Apr, 2015 - Comments: 0

In an intelligent electronic system, unexpected errors can lead to unplanned, unexpected behavior. This can be a potentially dangerous proposition for, say, an automotive manufacturer, as well as a costly occurrence for consumer product developers. Compliance to the latest safety standards can be a laborious, time-consuming process. Fortunately, there are now technologies available that can aut... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

5 Issues Under The Foundry Radar
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

In the foundry business, the leading-edge segment grabs most, if not all, of the headlines. Foundry vendors, of course, are ramping up 16nm/14nm finFET processes, with 10nm and 7nm in R&D. The leading-edge foundry business is sizable, but it’s not the only thing going on in the competitive arena. In fact, there are battles taking place in many other foundry segments, such as 2.5D/3D packag... » read more

Ecosystem Changes
By Ed Sperling - 26 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

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